HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing

The centralized methods for connection allocation in a circuit-switched network-on-chip (NoC) based on time-division multiplexing (TDM) may pose serious performance and scalability issues in large-scale networks due to the 1) limited path search speed, 2) increasing allocation request rate at central unit and 3) the increasing communication cost between the central unit and NoC nodes. This paper tackles this problem by proposing a combined centralized-distributed approach that splits the original NoC into multiple non-overlapping logical partitions, each of them served by a dedicated NoC-Manager unit. The NoC-Manager employs fast trellis-search shortest path algorithm enabling local path search inside the associated NoC partition, while a set of NoC-Managers jointly combine the partial results in a distributed manner in order to find the most likely global path. This approach attempts to combine the benefits of distributed and centralized systems, whilst the experimental results demonstrate its high potential regarding performance and scalability improvement.

This article proposes a circuit-switched router that combines Spatial Division Multiplexing (SDM) and Time Division Multiplexing (TDM) in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing contention in the network. Furthermore, Quality of Service (QoS) is easily guaranteed. The proposed router was synthesized on an Stratix III 3SL340F FPGA device. A 4 × 4 2D Mesh SDM-TDM Network-on-Chip (NoC) was built with the proposed router and synthesized on the 3SL340F FPGA device. The 4 × 4 2D Mesh SDM-TDM NoC was used to build on an FPGA device, a Multiprocessor System-on-Chip (MPSoC) platform consisted of 16 Nios II/f processors, 16 20-KB On-chip Memories, and 16 Network Interfaces. Synthesis results of the MPSoC platform show that the proposed router architecture can be used to built large practicable MPSoC platforms with the proposed NoC architecture with a reasonable hardware overhead and appreciable clock frequency. Simulation results show that combining SDM and TDM techniques in a router allows the highest probability of establishing paths through the network.

NoC (Network on Chip) architecture exploration is an up to date problem with today's multimedia applications and platforms. The presented methodology gives a solution to easily evaluate timing and resource performances tuning several architectural parameters, in order to find the appropriate NoC architecture with a unique emulation platform. In this paper, a design flow that generates NoC-based emulation platforms on FPGA is presented. From specified traffic scenarios, our tool automatically inserts appropriate IP blocks (emulation blocks and routing algorithm) and generates an RTL NoC model with specific and tunable components that is synthesized on FPGA.

The evaluation of Network-On-Chip (NoC) architectures is an up to date problem in the design of System-on-Chip. Emulation on FPGA (Field Programmable Gate Array) is used to cover all possible NoC solutions in a reduced exploration time. Emulation requires multi-FPGA platform as the resources for large NoC is important and cannot be handling by one FPGA. In the same time, SoC community is exploring 3D technology for the next generation of large SoC with 3D NoC, making emulation more complex. This paper presents a case study of the deployment of the 2D NoC structure to 3D. A design flow is proposed for the automatic generation of a NoC targeting 3D on multi-FPGAs. The flow integrates emulation blocks used for the validation and exploration on the NoC. With this automatic aided tool, the designer can evaluate and explore the NoC architecture and extract performances of the NoC regardless of the multi-component platform. One may expect a communication performance improvement using an adapted partitioning of the NoC, as highlighted by the results given in this paper.

This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits -- all with the same bandwidth -- between all nodes. This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented. The static schedule makes the NoC time-predictable and enables worst-case execution time analysis of communicating real-time tasks.

With Moore’s law supplying billions of transistors, and uniprocessor architectures delivering diminishing performance, multicore chips are emerging as the prevailing architecture in both general-purpose and application-specific markets. As the core count increases, the need for a scalable on-chip communication fabric that can deliver high bandwidth is gaining in importance, leading to recent multicore chips interconnected with sophisticated on-chip networks. In this chapter, we first present a tutorial on on-chip network architecture fundamentals including on-chip network interfaces, topologies, routing, flow control, and router microarchitectures. Next, we detail case studies on two recent prototypes of on-chip networks: the UT-Austin TRIPS operand network and the Intel TeraFLOPS on-chip network. This chapter organization seeks to provide the foundations of on-chip networks so that readers can appreciate the different design choices faced in the two case studies. Finally, this chapter concludes with an outline of the challenges facing research into on-chip network architectures.KeywordsOutput PortVirtual ChannelMulticore SystemVery Long Instruction WordSleep TransistorThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

NoC designs can be accepted to provision general communications between multiple IPs above multi-processor schemes on chip. In this effort we demonstrate the forming and imitation based exploration of some current architectures intended for Network on Chip (NoC). Specifically in this paper focus on the time synchronization based network, it hasthe Routing Integrated Time Synchronization protocol (RITS) that integrates post-facto time sync into a routing service also its achieved high result for QoS improvement in network. RITS, as well as reactive techniques in general, is superior to many proactive time sync protocols with respect to communication overhead. The best effort (BF) analysis of a representative reactive technique, the Routing Integrated Time Synchronization protocol (RITS) shows that in the general case, the presence of slack time cause RITS to Guaranteed throughput with the size of the network. We have using a shortest path based Traffic aware algorithm to time based data transmission quickly and efficiently on their network. It has more secure and easy to transfer data from one mobile node to another mobile node on the network.

A general purpose processor used to consist of a single processing core, which performed and controlled all tasks on the chip. Due to the continuous increase of the number of transistors available on-chip and the operational clock frequency, it became impossible to reach every function within the chip in a single clock cycle. Furthermore, centralized control became hard with the increase in functionality. This lead to the current move towards integrating a set of independent processing cores into a single chip. These multi-core architectures rely on a well designed on-chip communication architecture. Global wires and bus-based systems need to be replaced to overcome the problem of wiring and the single point of arbitration. This is introduced as the Network-on-Chip (NoC) paradigm. In this work we explore the paradigm by implementation and characterization of multiple NoC router architectures. The scope of the communication architecture is the embedding in a heterogeneous multi-core System-on-Chip for streaming applications. Based on application analysis we propose a circuit switched router architecture and improve an existing packet switched router architecture that also oers QoS. The two routers are compared in-depth with two other packet switched router design on both latency and energy performance. Furthermore, to speed-up cycle and bit-accurate simulations, we developed a framework for large many-core architectures on a single FPGA using a sequential simulation approach.

Network delay is a major design parameter for Networks-on-Chip (NoC)-based applications. Improving NoC delay could be achieved at different design phases. At the system level, we study in this paper the impact of the network topology on NoC system delay using graph-theoretic concepts. A topology-based model is developed to calculate the average NoC delay, which is caused by links and routers. The proposed model could be used to select the optimal topology that achieves the minimum network delay for a given NoC application. A case study is presented to show how this model could be used to improve the delay of a given NoC application at early design phases.

Advanced Artificial Intelligence (AI) systems that process vast feature sets can be designed using Deep Neural Networks (DNN). The popularity and prevalence of DNN based tasks are mainly due to their ability to achieve state of the art accuracy. However, DNN based systems are computationally intensive with heavy on-chip and off-chip data movement demands. Efficient hardware accelerators with systematized interconnection platform support handling this insistent computation and fast communication requirements. With rise in accelerator complexity, it is important to identify and solve communication overheads imposed due to heavy data movement in the system. Need for increased data transfers come as a consequence of complex computations and structure of data storage hierarchy in different DNN models. Multi-core system with underlying Network on Chip (NoC) framework is a promising design choice for implementing DNN based systems with diverse layers. Data movement plays a vital role in deciding performance of such systems. Analysing metrics that affect latency and energy/power efficiency of system is thus crucial in deciding performance enhancement of these DNN inference accelerators. This paper quantifies the communication overheads associated with accelerating different DNN models which use NoC as its basic communication platform.

In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System on-Chip (SoC) application. We present several design choices and focus on the power optimization of the NoC while achieving the required performance. Our design steps include module mapping and allocation of customized capacities to links. Unlike previous studies, in which point-to-point, per-flow timing constraints were used, we demonstrate the importance of using the application end-to-end traversal latency requirements during the optimization process. In order to evaluate the different alternatives, we report the synthesis results of a design that meets the actual throughput and timing requirements of the commercial SoC. According to our findings, the proposed technique offers up to 40% savings in the total router area and a reduction of up to 49% in the inter-router wiring area.

In recent years, the rise in the number of cores being integrated on a single chip has led to a greater emphasis on scalable communication fabrics that can overcome data transfer bottlenecks. Network-on-Chip (NoC) architectures have been gaining widespread acceptance as communication backbones for multi-core systems, due to their high scalability, predictability, and performance. However, NoCs are also power hungry, and synthesizing a NoC fabric for a particular application requires solving a multitude of non-trivial design problems. Due to the large design space associated with various possible NoC configurations and design constraints, it is critical to automate the exploration process and arrive at a customized NoC that meets performance goals, while minimizing power and peak temperature. In this paper, we present a novel application specific NoC synthesis framework (POSEIDON) that combines multiple algorithms and heuristics to efficiently explore the solution space. Our results indicate that the proposed framework provides a reduction of up to 15.7% in power consumption, 21.08% in average latency, 27.05% in total energy, and 42.7% in energy-delay product compared to state-of-the-art approaches, as well as a 4.2% reduction in peak temperature when the framework is customized for thermal-aware synthesis.

Simulation environment for link energy estimation in networks-on-chip with virtual channels

A regression-based design space exploration methodology is proposed that models the impacts of the memory hierarchy and the network-on-chip (NoC) on the overall chip multiprocessor (CMP) performance. Designers cannot explore all possible designs for a NoC without considering interactions with the rest of the uncore, in particular the cache configuration and memory hierarchy which determine the amount and pattern of the traffic on the NoC. The proposed regression model is able to capture the salient design points of the uncore for a comprehensive design space exploration by designing memory and NoC-specific regression models and leveraging recent advances in uncore simulation. To show the utility of our methodology, Uncore RPD, two case studies are presented: i) analyzing and refining regression models for an 8-core CMP and ii) performing a rapid design space exploration to find best performing designs of a NoC-based CMP given area-constraints for CMPs of up to 64 cores. Through these case studies, it is shown that i) simultaneous consideration of the memory and NoC parameters in the NoC design space exploration can refine uncore-based regression models, ii) sampling techniques must consider the dynamic design space of the uncore, and iii) overall, the proposed regression models reduce the amount of simulations required to characterize the NoC design space by up to four orders of magnitude.

The conception of Network-on-Chip (NoC) presents system designers with a new approach to the design of on-chip interconnection structures. However, such networks present designers with a large array of design parameters and decisions, many of which are critical to the efficient operation of NoC systems. To aid the design process of complex systems-on-chip, this paper presents a NoC simulation environment that has been developed and implemented using SystemC, a transaction-level modeling language. The simulation environment consists of on-chip components as well as traffic generators, which can generate various types of traffic patterns. A set of simulation results demonstrates the types of parameters that can affect performance of on-chip systems, including topology, network latency and achievable throughput. The results also verify the modeling capabilities of the proposed environment.