Fledge: Flexible Edge Platforms Enabled by In-memory Computing

The traditional von Neumann architecture limits the increase in computing efficiency and results in massive power consumption in modern computers due to the separation of storage and processing units. The novel neuromorphic computation system, an in-memory computing architecture with low power consumption, is aimed to break the bottleneck and meet the needs of the next generation of artificial intelligence (AI) systems. Thus, it is urgent to find a memory technology to implement the neuromorphic computing nanosystem. Nowadays, the silicon-based flash memory dominates non-volatile memory market, however, it is facing challenging issues to achieve the requirements of future data storage device development due to the drawbacks, such as scaling issue, relatively slow operation speed, and high voltage for program/erase operations. The emerging resistive random-access memory (RRAM) has prompted extensive research as its simple two-terminal structure, including top electrode (TE) layer, bottom electrode (BE) layer, and an intermediate resistive switching (RS) layer. It can utilize a temporary and reversible dielectric breakdown to cause the RS phenomenon between the high resistance state (HRS) and the low resistance state (LRS). RRAM is expected to outperform conventional memory device with the advantages, notably its low-voltage operation, short programming time, great cyclic stability, and good scalability. Among the materials for RS layer, indium gallium zinc oxide (IGZO) has shown attractive prospects in abundance and high atomic diffusion property of oxygen atoms, transparency. Additionally, its electrical properties can be easily modulated by controlling the stoichiometric ratio of indium and gallium as well as oxygen potential in the sputter gas. Moreover, since the IGZO can be applied to both the thin-film transistor (TFT) channel and RS layer, it has a great potential for fully integrated transparent electronics application.In this work, we proposed amorphous transparent IGZO-based RRAMs and investigated switching behaviors of the memory cells prepared with different top electrodes. First, ITO was choosing to serve as both TE and BE to achieve high transmittance. A multi-target magnetron sputtering system was employed to deposit all three layers (TE, RS, BE layers) on glass substrate. I-V characteristics were evaluated by a semiconductor parameter analyzer, and the bipolar RS feature of our RRAM devices was demonstrated by typical butterfly curves. The optical transmission analysis was carried out via a UV-Vis spectrometer and the average transmittance was around 80% out of entire devices in the visible-light wavelength range, implying high transparency. We adjusted the oxygen partial pressure during the sputtering of IGZO to optimize the property because the oxygen vacancy concentration governs the RS performance. Electrode selection is crucial and can impact the performance of the whole device. Thus, Cu TE was chosen for our second type of device because the diffusion of Cu ions can be beneficial for the formation of the conductive filament (CF). A ~5 nm SiO2 barrier layer was employed between TE and RS layers to confine the diffusion of Cu into the RS layer. At the same time, this SiO2 inserting layer can provide an additional interfacial series resistance in the device to lower the off current, consequently, improve the on/off ratio and whole performance. Finally, an oxygen affinity metal Ti was selected as the TE for our third type of device because the concentration of the oxygen atoms can be shifted towards the Ti electrode, which provides an oxygengettering activity near the Ti metal. This process may in turn lead to the formation of a sub-stoichiometric region in the neighboring oxide that is believed to be the origin of better performance.In conclusion, the transparent amorphous IGZO-based RRAMs were established. To tune the property of RS layer, the sputtering conditions of RS were varied. To investigate the influence of TE selections on switching performance of RRAMs, we integrated a set of TE materials, and a barrier layer on IGZO-based RRAM and compared the switch characteristics. Our encouraging results clearly demonstrate that IGZO is a promising material in RRAM applications and breaking the bottleneck of current memory technologies.

A review on selective in-memory computing processors: Potential alternative to AI-driven applications

An efficient read approach for memristive crossbar array

Flexible memory devices have continued to attract more attention due to the increasing requirement for miniaturization, flexibility, and portability for further electronic applications. However, all reported flexible memory devices have binary memory characteristics, which cannot meet the demand of ever-growing information explosion. Organic resistive switching random access memory (RRAM) has plenty of advantages such as simple structure, facile processing, low power consumption, high packaging density, as well as the ability to store multiple states per bit (multilevel). In this study, we report a small molecule-based flexible ternary memory device for the first time. The flexible device maintains its ternary memory behavior under different bending conditions and within 500 bending cycles. The length of the alkyl chains in the molecular backbone play a significant role in molecular stacking, thus guaranteeing satisfactory memory and mechanical properties.

As the demand for artificial intelligence continues to grow, there is a need for specialized hardware that can efficiently process and power AI algorithms. This is where VLSI (Very Large-Scale Integration) design comes into play. By integrating millions, or even billions, of transistors onto a single chip, VLSI design enables the creation of powerful AI-integrated circuits. However, designing hardware specifically for artificial intelligence poses its own set of challenges. The complexity of AI algorithms and the need for parallel processing capabilities demand innovative solutions. VLSI designers must carefully consider factors such as power consumption, heat dissipation, and the integration of specialized neural network accelerators. In addition to these considerations, VLSI designers must also address the scaling limitations of semiconductor technology. As AI algorithms become more complex, the demand for advanced VLSI architecture increases. Designers must find ways to enhance transistor density and performance while overcoming the limitations imposed by the physical laws governing semiconductor manufacturing. In-Memory Computing (IMC) is an emerging paradigm designed to overcome the limitations of the traditional Von Neumann architecture, particularly for energy-efficient AI applications. Traditional computing systems suffer from the "memory wall"—a bottleneck caused by the constant transfer of data between the CPU and memory. This leads to inefficiencies in latency, bandwidth, and energy consumption, especially for AI tasks which involve huge volumes of matrix operations and data movement. Keywords: Very Large-Scale Integration (VLSI), Artificial Intelligence (AI), In-memory computing (IMC), Neuromorphic, multiply-and-accumulate (MAC), RRAM (Resistive RAM), MRAM (Magnetoresistive RAM), PCM (Phase-Change Memory), FeFET (Ferroelectric FET), spiking neural networks (SNNs)

The rapid progress in artificial intelligence (AI) is driving the need for more efficient computing architectures capable of performing the demanding, repetitive computations required for processing large datasets. Unlike traditional von Neumann architectures, which separate processing and memory units, new approaches aim to integrate computational capabilities directly into memory arrays, facilitating in-memory computing (IMC). This integration significantly improves both energy efficiency and processing speed, particularly for AI and similar applications. A crucial operation within IMC is vector-matrix multiplication (VMM), where input signal vectors interact with a memory state matrix to produce output signal vectors.One innovative approach to implementing VMM is through the use of a ferroelectric Hf₀.₅Zr₀.₅O₂ (HZO) layer in conventional field-effect transistor (FET) or metal-insulator-metal (MIM) devices. These HZO-based ferroelectric components show significant promise for low-power, IMC-compatible systems, especially when integrated into MIM capacitor structures. Their simple fabrication process supports scalable system integration, while offering benefits such as low power consumption and high reliability. However, current IMC techniques utilizing ferroelectric MIM capacitors rely on small-signal capacitance readout, which suffers from limited contrast between high and low capacitance states, making it difficult to distinguish memory states effectively for efficient IMC operations.In this study, we introduce two novel readout techniques to improve the scalability and robustness of IMC, focusing on enhanced memory differentiation by reading the ferroelectric remanent polarization (Pᵣ) instead of relying on small-signal capacitance. These methods exploit the switching behavior between two stable polarization states (Pₗₒʷ and Pᵤₚ) of the HZO material. To measure charge accumulation resulting from polarization switching, we connect the ferroelectric HZO capacitors in series with either a shunt resistor (Rₛₕᵤₙₜ) or an external capacitor (Cₑₓt) to produce current or voltage signals, respectively. Both readout methods show significantly improved memory differentiation and VMM performance compared to the traditional small-signal capacitance approach. For example, in the current readout method, the maximum displacement current in the high-current state (Iₛʷ + Iₙₒₙ-ˢʷ) is approximately 0.31 mA, while the low-current state (Iₙₒₙ-ˢʷ) is about 0.04 mA when no switching current is present. Notably, the static leakage current during the input pulse is nearly zero, underscoring the potential for low-power operation in capacitive systems. In the voltage readout method, an initial Pᵤₚ state leads to a high output voltage (Vₒᵤₜ) of approximately 0.13 V, while an initial Pₗₒʷ state produces a low Vₒᵤₜ of about 0 V. These polarization-based readout techniques provide substantially higher memory distinction and better VMM performance compared to traditional small-signal capacitance methods.We will demonstrate IMC systems by using voltage readout of the Pr change in HZO layers, employing charge compensation between the Cext and HZO capacitors. This method takes advantage of the superior memory distinction within the capacitive system, offering more reliable and lower-power performance compared to traditional Fe-FET approaches.The authors acknowledge Prof. Joseph S. Friedman and Dr. Peng Zhou for the technical discussion.

Resistive random-access memory (RRAM) devices that can execute logic are promising for in-memory computing. In state-of-the-art, a complementary resistive switch (CRS) bit-cell of two back-to-back bipolar RRAM shows a universal logic gate by multiple sequential write/compute operations using a resistance-based input/output (R-R logic) along with an extra read cycle. Here, we propose and experimentally demonstrate a three-terminal RRAM (3T-RRAM) to enable logic operations with voltage input and resistance output (V-R logic) in a single device and single write/compute cycle without a dedicated read cycle. Essentially, a nanoscale (~20nm) side-contact is added to a typical two-terminal Pt/Pr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ca <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> MnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (PCMO)/W RRAM. As the PCMO RRAM is non-filamentary, all the terminals can act as in-out terminals. Hence, we utilize the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> terminal to read the state of the device while the other two terminals simultaneously performing the logic operation. Finally, we demonstrate the Implication (IMP) and converse IMP logic operations using 3T-RRAM. Such a device can enable area and energy-efficient in-memory computation.

Resistive random access memory (ReRAM) devices are considered to be one of the most promising candidates for the next generation of nonvolatile memory devices because of their superior properties such as low power consumption, simple structure, high integration density, and fast operation speed. In this study, we used zinc oxide (ZnO) thin films to fabricate ReRAM devices comprising Au/ZnO/Al and Al/Au/ZnO/Al structures. We observed that the operating stability of the device containing the Al/Au/ZnO/Al structure improved. The devices displayed effective and stable operational characteristics. The operational voltage of the ZnO ReRAM devices was less than 3 V, and the reset operational voltage was less than −1.5 V.

Resistance random access memory (RRAM) based on resistive switching in metal oxides has attracted considerable attention as a promising candidate for next-generation nonvolatile memory due to its high operating speed, superior scalability, and low power consumption. However, some operating parameters of RRAM cannot meet the practical requirement, which impedes its commercialization. A lot of experimental results show that doping is an effective method of improving the performance of RRAM, while the study on the physical mechanism of doping is rare. It is generally believed that the formation and rupture of conducting filaments, caused by the migration of oxygen vacancies under electric field play a major role in resistive switching of metal oxide materials. In this work, the first principle calculation based on density functional theory is performed to study the effects of transition metal element X (X=Mn, Fe, Co, and Ni) doping on the migration barriers and formation energy of oxygen vacancy in ZnO. The calculation results show that the migration barriers of both the monovalent and divalent oxygen vacancy are reduced significantly by Ni doping. This result indicates that the movement of oxygen vacancies in Ni doped ZnO is easier than in undoped ZnO RRAM device, thus Ni doping is beneficial to the formation and rupture of oxygen vacancy conducting filaments. Furthermore, the calculation results show that the formation energy of the oxygen vacancy in ZnO system can be reduced by X doping, especially by Ni doping. The formation energy of the oxygen vacancy decreases from 0.854 for undoped ZnO to 0.307 eV for Ni doped ZnO. Based on the above calculated results, Ni doped and undoped ZnO RRAM device are prepared by using pulsed laser deposition method under an oxygen pressure of 2 Pa. The Ni doped ZnO RRAM device shows the optimized forming process, low operating voltage (0.24 V and 0.34 V for Set and Reset voltage), and long retention time (&gt;104 s). Set and Reset voltage in Ni doped ZnO device decrease by 80% and 38% respectively compared with those in undoped ZnO device. It is known that the density of oxygen vacancies in the device is dependent on the oxygen pressure during preparation. The Ni doped ZnO RRAM device under a higher oxygen pressure (5 Pa) is also prepared. The Ni doped ZnO RRAM device prepared under 5 Pa oxygen pressure shows a little higher Set and Reset voltage than the device prepared under 2 Pa oxygen pressure, while the operating voltages are still lower than those of undoped ZnO RRAM. Thus, the doping effect in the ZnO system is affected by the density of oxygen vacancies in the device. Our work provides a guidance for optimizing the performance of the metal oxide based RRAM device through element doping.

Realization of spiking neural network (SNN) hardware with high energy efficiency and high integration may provide a promising solution to data processing challenges in future internet of things (IoT) and artificial intelligence (AI). Recently, design of multi-core reconfigurable SNN chip based on resistive random-access memory (RRAM) is drawing great attention, owing to the unique properties of RRAM, e.g., high integration density, low power consumption, and processing-in-memory (PIM). Therefore, RRAM-based SNN chip may have further improvements in integration and energy efficiency. The design of such a chip will face the following problems: significant delay in pulse transmission due to complex logic control and inter-core communication; high risk of digital, analog, and RRAM hybrid design; and non-ideal characteristics of analog circuit and RRAM. In order to effectively bridge the gap between device, circuit, algorithm, and architecture, this paper proposes a simulation model—FangTianSim, which covers analog neuron circuit, RRAM model and multi-core architecture and its accuracy is at the clock level. This model can be used to verify the functionalities, delay, and power consumption of SNN chip. This information cannot only be used to verify the rationality of the architecture but also guide the chip design. In order to map different network topologies on the chip, SNN representation format, interpreter, and instruction generator are designed. Finally, the function of FangTianSim is verified on liquid state machine (LSM), fully connected neural network (FCNN), and convolutional neural network (CNN).

In-Memory Computing (IMC) provides an alternative to conventional von-Neumann-based architectures by performing computation directly within memory, thus significantly reducing data movement. Resistance Random Access Memory (RRAM) crossbar array are explored for in-memory computing (IMC). A hybrid platform with bit-sliced MAC architecture and RRAM crossbar array is proposed here to perform in-memory computing. This paper presents a 4x4 PMO-based a RRAM crossbar array with an FPGA for controlling data flow and showing its utility for complete MAC operation. The RRAM array stores the data, while the FPGA sends the input signal and does the post-processing after the data passes through the RRAM array. Such architectures hold strong promise for ultra-low-power AI applications in wearables, edge sensing, and portable analytics.

Spintronic devices for high-density memory and neuromorphic computing – A review

In the rapidly evolving landscape of modern electronics, memory devices and circuits play a pivotal role in determining system performance, energy efficiency, and scalability. Traditional memory technologies, such as Dynamic Random Access Memory (DRAM) and NAND flash, face challenges related to scaling limits, latency, power consumption, and endurance, particularly as demands for faster and more efficient data storage grow. Emerging non-volatile memory (NVM) technologies like Resistive Random Access Memory (ReRAM), Phase-Change Memory (PCM), and Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) offer potential solutions to these challenges, but their combination into existing systems poses design and manufacturing hurdles. The primary problem lies in balancing storage performance with power efficiency while ensuring scalability for advanced applications such as artificial intelligence (AI), Internet of Things (IoT), and high-performance computing (HPC). Innovations in circuit design, including advanced error-correction mechanisms, adaptive voltage scaling, and low-power architectures, are critical in enhancing the overall performance of memory systems. This study employs a hybrid approach, combining novel circuit design techniques with the combination of emerging NVM technologies. Simulations were performed to evaluate the performance metrics, including write latency, energy consumption, and endurance. Results show that ReRAM-based memory designs achieved a 35% reduction in write latency and a 50% improvement in energy efficiency compared to traditional DRAM, while PCM demonstrated superior endurance with up to 10^8 write cycles. Furthermore, STT-MRAM circuits showed promise with a 40% reduction in standby power consumption. These advancements in memory circuits and devices highlight the potential for significant improvements in storage performance and efficiency, addressing the growing needs of modern electronic systems and paving the way for future innovations in computing.

Resistive random access memory (RRAM) has attracted as candidate in the next generation of non-volatile memory device due to its low power consumption, fast write/erase speed, and high CMOS compatibility 1–3. At present, among various materials, metal-organic frameworks (MOFs) are significantly attracting attention as promising materials for data storage applications due to their advantages of highly ordered pores, large surface area, tunable structure, and subsequent controllable function 4–6. However, it is difficult to apply MOF to RRAM, because synthesis time is generally long and additional step is needed to form the MOF into a thin film. Therefore, there is a need for a new method for synthesizing MOF in the form of a thin film simply and fast. In this work, we simply and fast synthesized a 2D MOF nanosheets, Cu(BDC), in the form of thin film using laser process. The dissolved ligand (terephthalic acid) in the N,N-dimethylformamide (DMF) is dropped on the Cu thin film and then irradiate the laser beam on the active spot. Photon energy of laser is absorbed in the Cu metal film, which generate the photothermal effect. This photothermal effect oxides the Cu atom into Cu ion and the oxidized Cu ions are used as metal source of Cu(BDC). This process simply and quickly transforms the Cu thin film into a Cu(BDC) thin film that can act an active layer of RRAM. The suggested method not only is finished in minutes, but also does not needed additional process step of transferring the MOF onto the thin film. The fabricated 2D MOF based-RRAM shows a typical bipolar switching behavior. Our device also exhibits a high on/off ratio (>103), low set/reset voltages (1 V > in SET and -0.5 V > in RESET), and long retention (1×104 s). Therefore, our research suggests a simple and rapid synthesis method of MOFs in the form of a thin film by using laser process and demonstrates applicability 2D MOF fabricated by laser process for the non-volatile memory device. Figure Caption Figure (a) Schematics of synthesis of metal-organic frameworks (MOFs) using laser process. (b) Scanning electron microscopy (SEM) image of Cu(BDC) thin film surface. (c) Transmission electron microscopy (TEM) image of single Cu(BDC) nanosheet. (d) Current-voltage (I-V) curve for 2D MOF based-RRAM device. (e) Retention tests of 2D MOF based-RRAM device. Figure 1

The rapid advancements in artificial intelligence (AI) have demonstrated great success in various applications, such as cloud computing, deep learning, and neural networks, among others. However, the majority of these applications rely on fast computation and large storage, which poses significant challenges to the hardware platform. Thus, there is a growing interest in exploring new computation architectures to address these challenges. Compute-in-memory (CIM) has emerged as a promising solution to overcome the challenges posed by traditional computer architecture in terms of data transfer frequency and energy consumption. Non-volatile memory, such as Quantum-dot transistors, has been widely used in CIM to provide high-speed processing, low power consumption, and large storage capacity. Matrix-vector multiplication (MVM) or dot product operation is a primary computational kernel in neural networks. CIM offers an effective way to optimize the performance of the dot product operation by performing it through an intertwining of processing and memory elements. In this paper, we present a novel design and analysis of a Quantum-dot transistor (QDT) based CIM that offers efficient MVM or dot product operation by performing computations inside the memory array itself. Our proposed approach offers energy-efficient and high-speed data processing capabilities that are critical for implementing AI applications on resource-limited platforms such as portable devices.