Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits

This paper examines the performance of differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices. Both device types have L/sub eff/=0.15 /spl mu/m. The top and bottom gates of the dual-gate device are self-aligned to the source/drain, and the device has a fanned-out source/drain structure with low parasitic resistance. The dual-gate device current drive and transconductance are about 2.2 times that of a partially-depleted device at the same bias. We compared three differential static CMOS topologies: (a) standard CMOS logic; (b) push-pull cascode logic (PPCL), a low power high speed static logic topology; (c) complementary pass-transistor logic (CPL), known for its efficiency for device use and popular for fast arithmetic operations. We considered three cases: (a) partially-depleted device with standard bulk-like connection where the body is tied to the supply rail; (b) partially-depleted device with floating body (FB); (c) dual gate (DG) device where the bottom gate is driven with the top gate simultaneously. Based on a methodology described previously (Tretz et al. Proc. IEEE Midwest Symp. on Circuits and Systems, pp. 179-82, 1996), performance comparison of these topologies is sufficient to establish the relative performance of almost any other differential static CMOS topology, using the generic differential CMOS static gate concept. All differential static circuits can be described as a variation of the generic differential static gate comprised of pull-up and pull-down switches, cross-coupled elements, additional resistive loads, and active paths to V/sub dd//GND.

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. It can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4-bit multiplier proved that 70% power dissipation reduction was achieved, with 30% area overhead, and no reduction in the circuit speed.

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. The proposed technique can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, and without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4 bit multiplier proved that 30% power dissipation reduction was achieved, with 5% area overhead, and no reduction in the circuit speed.

A new pass-transistor logic called the current-sensing complementary pass-transistor logic tree (CSCPTL) is proposed and investigated. The new logic circuit can be used in low-voltage low-power systems for high-speed applications. To examine the low-voltage applications, a 1.2 V supply voltage is selected for one battery back-up systems. The current-sensing scheme yields a good sensing speed with small voltage swing. The dc power dissipation of the current mode circuit makes it difficult to apply in low power applications. The new circuit can resolve the dc power problem in the current-sensing scheme. The new circuit has superior speed performance with a power-delay product comparable to LCPL which is acknowledged to have the most potential in low-voltage low-power digital circuits design. The CSCPTL can be operated at 1.2 V without changing the conventional 5 V CMOS process.

A 64-bit low threshold voltage conditional carry adder using complementary pass-transistor logic for low-voltage and high-speed application was presented. The improved conditional sum addition rule can reduce the number of internal nodes and multiplexers in the adder design. And reducing the threshold voltage increases the speed of operation. Thus, a low threshold voltage design is favourable for implementing low-voltage, high-speed arithmetic systems. The performances of such circuits are compared with that of normal and zero threshold voltage schemes; the proposed circuit gets the lowest power-delay product and energy-delay product from 1.0V to 2.5V. The circuit is demonstrated to balance between power consumption and performance effectively.

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 /spl mu/m CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V. >

In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.

This paper presents low-power complementary pass-transistor adiabatic logic (CPAL) using two-phase power-clocks instead of four-phase ones. The two-phase CPAL uses complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. It is more suitable for design of flip-flops and sequential circuits, as it uses fewer transistors than conventional CMOS transmission gate-based implementations and other adiabatic logic circuits such as 2N-2N2P. Adiabatic flip-flops (D, T and JK) based on the two-phase CPAL are introduced. A practical sequential system realized with the proposed adiabatic flip-flops is demonstrated. SPICE simulations show that the two-phase CPAL flip-flops consume less power than 2N-2N2P and CMOS implementation.

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.

This paper presents PD-SOI SPICE, which is based on compact BiCMOS charge-control models and includes second-order effects, electron and lattice temperatures, for circuit simulation of low-voltage CMOS circuits using deep-submicron partially-depleted (PD) SOI CMOS devices. This PD-SOI SPICE performs transient simulation of the write-access critical path in an SRAM composed of 42 PD SOI CMOS devices without convergence problems, which are commonly encountered while modeling PD devices due to kink effects.

Reports a novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique., Using the ADTPT technique to dynamically control the body bias of the pass-transistor via only one auxiliary transistor, the new SOI CMOS complementary pass-transistor logic (CPL) circuit provides superior speed performance at a low supply voltage as compared to the conventional pass-transistor logic circuits without the ADTPT technique as verified by the MEDICI simulation results. The ADTPT technique is especially effective for use in CPL circuits with serially-connected multiple inputs.

The electrical performance of high-precision analog and digital circuits in MOSFETs is highly sensitive to temperature changes. Here, by studying the stability of electrical characteristics such as OFF-state leakage current, saturation current, and transconductance efficiency of fully depleted silicon-on-insulator (FDSOI) and partially depleted silicon-on-insulator (PDSOI) in the temperature range of 25 °C–300 °C, we proposed a new semiconductor-parameter-temperature-increment (SPTI) model. Within this SPTI model, it can clarify the influence of high-temperature electrical parameters, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha _{T}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta _{T}$ </tex-math></inline-formula> , on the stability of the electrical characteristics of FDSOI and PDSOI. Thus, it helps in understanding the differences in the stability of electrical characteristics between the two devices. In addition, the SPTI model can also be used to obtain the design domain of the electrical characteristics for FDSOI and PDSOI. More importantly, a compromise method based on the design parameter <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> can be obtained to effectively improve the electrical characteristics and the stability of the two devices.

We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

Today, the major limitation of designing of high-speed integrated circuits (ICs) with conventional technology is the delay limiting the switching speed of the gates. As evident from already established logic styles like complementary pass transistor logic (CPL), differential cascode voltage swing logic (DCVSL), etc., the circuit exploits the property of noise reduction due to differential inputs. Ideally current mode circuits have constant current gain with no input impedance and finite output impedance. The current gain of the circuit is set to unity as current amplification leads to higher consumption of static power. MOS current mode logic (MCML) is graced with certain advantages which include low level of noise generation, static power dissipation independent of switching activity, low voltage swing, a weak dependence of propagation delay on fan-out load capacitance, lower power dissipation at higher frequencies, etc., out way the few disadvantages such as elaborated design process and increased number of design parameters. In this paper, we present an in-depth study of MCML base approach in which the analysis of low-power applications is performed at the target data rate of 1 Gbps. Work has been done on a standard CMOS technology of 0.18 μm.

This paper explores different Full adder techniques such as Transmission Gate(TG) logic, Complementary pass transistor logic(CPL), Complementary metal oxide semiconductor(CMOS), Gate diffusion input (GDI) and Modified GDI (Gate Diffusion Input) logic. The main objective is find full adders providing low powered and high-speed with good voltage swing. GDI (Gate Diffusion Input) is one of the area effective, high speed and low power technique. It needs smallest amount of transistors as compared to conventional CMOS technology. But the drawback of GDI (Gate Diffusion Input) is that its output has poor logic swing. Modified Gate diffusion technique overcomes this problem.