Implementation and evaluation of the Complex Streamed Instruction set

Stroke is a leading cause of disability and impaired arm function is a common consequence. Constraint-induced movement treatment is a technique used to increase weak arm use and to decrease motor deficits resulting from stroke. Eleven stroke survivors participated in a constraint-induced movement treatment protocol of 3 ½ hours of treatment per day for 8 days. Participants experienced significantly increased use of the weak arm in daily activities, which was measured by the Motor Activity Log, and a trend toward improved coordination in the weak arm, which was measured by the Wolf Motor Function Test. Participants did not report significant improvements in average performance or satisfaction in self-identified occupational performance problems. When these problems were analyzed individually, no significant differences were seen immediately post-treatment. However, significant improvements were seen for satisfaction at 4 to 6 months post-treatment. The occupational performance problems identified by the participants were equally divided between problems related to hand use and problems not related to hand use. Approximately half of the non-hand use problems involved endurance. Although participants in this study did make improvements in arm use and coordination, they did not identify improvements in average occupational performance or satisfaction as an outcome of constraint-induced movement treatment.

In a microprogrammed digital computer, the instructions are carried out in two stages—an instruction set is fetched from the main memory; is decoded and then a sequence of microoperations is performed by returning the control to a particular location of the control memory containing the microprogramme. The instruction sets are specified in terms of the required microoperations and the definite precedence relations. In this paper, an algorithm has been described to find out an optimal specification of the microprogramme control memory of a digital computer, given the total set of distinct instructions to be executed by the system. The objective of the algorithm has been to minimize the cost of implementation in terms of the total number of bits in the control memory. A loop-free structure of the microprogramme has been assumed, and multiple occurrence of a single micro-event in a single instruction set has been allowed.

We propose efficient schemes for information-theoretically secure key exchange in the Bounded Storage Model (BSM), where the adversary is assumed to have limited storage. Our schemes generate a secret One Time Pad (OTP) shared by the sender and the receiver,from a large number of public random bits produced by the sender or by an external source. Our schemes initially generate a small number of shared secret bits, using known techniques. We introduce a new method to expand a small number of shared bits to a much longer, shared key.Our schemes are tailored to the requirements of sensor nodes and wireless networks. They are simple, efficient to implement and take advantage of the fact that practical wireless protocols transmit data in frames, unlike previous protocols, which assume access to specific bits in a stream of data. Indeed, our main contribution is twofold.On the one hand, we construct schemes that are attractive in terms of simplicity, computational complexity, number of bits read from the shared random source and expansion factor of the initial key to the final shared key.On the other hand, we show how to transformany existing scheme for key exchange in BSM into a more efficient scheme in the number of bits it reads from the shared source, given that the source is transmitted in frames.

Cochlear Implantation in Inner Ear Malformations: Systematic Review of Speech Perception Outcomes and Intraoperative Findings.

Outdoor air ventilation rates vary considerably between and within buildings, and may be too low in some spaces. The purpose of this study was to evaluate the potential work performance benefits of increased ventilation. We analyzed the literature relating work performance with ventilation rate and employed statistical analyses with weighting factors to combine the results of different studies. The studies included in the review assessed performance of various tasks in laboratory experiments and measured performance at work in real buildings. Almost all studies found increases in performance with higher ventilation rates. The studies indicated typically a 1-3% improvement in average performance per 10 l/s-person increase in outdoor air ventilation rate. The performance increase per unit increase in ventilation was bigger with ventilation rates below 20 l/s-person and almost negligible with ventilation rates over 45 l/s-person. The performance increase was statistically significant with increased ventilation rates up to 15 l/s-person with 95% CI and up to 17 l/s-person with 90% CI. Practical Implications We have demonstrated a quantitative relationship between work performance and ventilation within a wide range of ventilation rates. The model shows a continuous increase in performance per unit increase in ventilation rate from 6.5 l/s-person to 65 l/s-person. The increase is statistically significant up to 15 l/s-person. This relationship has a high level of uncertainty; however, use of this relationship in ventilation design and feasibility studies may be preferable to the current practice, which ignores the relationship between ventilation and productivity.

IA21: Risk prediction models for lung cancer

This paper describes the performance advantages of a two and four byte variable length instruction set, Thumb2. over a four byte fixed length instruction set, ARM. Both instruction sets are found in ARMv7-A ISA compatible processors, such as the ARM Cortex-A8 and Cortex-A9. The code size reduction when using a variable length instruction set is well understood and can be significant. The focus of this paper is the performance advantage of increased code density. With Thumb2 more instructions are stored in the I-cache, increasing I-cache hit rates, and in turn increasing the performance of the processor. To demonstrate the performance advantage of Thumb2, a Mozilla based web browser built for Thumb2 and ARM on Linux is run in a full system emulator and in a full system instruction set simulator with a cache model. Switching from the ARM four byte fixed length instruction set to the Thumb2 two and four byte variable length instruction set results in a 1.07x improvement in performance and 33% improvement in code density.

In this study, we develop a novel error detection algorithm for Lempel-Ziv-77 (LZ77) compressed data. In the proposed algorithm, additional bits are not used to detect bit errors, unlike in conventional methods such as checksum, cyclic redundancy check, Hamming code, and repetition code. We also introduce eight special features of LZ77-compressed data for detecting the presence of errors. We demonstrate the feasibility of the algorithm based on simulations and evaluate it using two publicly available databases comprising the Calgary and Canterbury corpora. The error detection rate using the proposed algorithm is below those of conventional methods, but the compression ratio is better. The application of a parity bit in the algorithm improves the error detection performance. The number of redundant bits increases owing to the insertion of the parity bit, but the code rate is still greater than or equal to 0.9, whereas conventional methods obtain code rates less than 0.9. Simulations demonstrate that the algorithm obtains significant performance improvements when a parity bit is periodically inserted. In particular, we achieve an error detection rate of 100% using the parity bit when the number of bit errors is greater than seven.

In this work, the creation of a dataset labeled in a pixel-wise manner for the uncommon domain of stain detection on patterned laundry is described. The unique properties of images in this dataset—stains are small and sometimes occur in large amounts—led to the creation of noisy labels. Indeed, the training of a fully convolutional neural network for salient object detection with this dataset revealed that the model predicts stains missed by human labelers. Thus, the reduction in label noise by adding overlooked regions with the help of the model’s predictions is examined in two different experiments. In the model-assisted labeling experiment, a simulation is ran where a human selects correct regions from the predictions. In the self-training experiment, regions of high certainty are automatically selected from the predictions. Re-training the model with the revised labels shows that model-assisted labeling leads to an average improvement in performance by 8.52%. In contrast, with self-training, the performance increase is generally lower (2.58% on average) and a decrease is even possible since regions of high certainty are often false positives.

Multilevel modulation schemes have variations in bit-reliabilities and each has different symbol reliabilities. Choosing the modulation scheme which has the greatest symbol reliability at target SNR on retransmissions offers more chances to get higher Hybrid ARQ performance by making the sum of total bit-reliabilities greater in the entire decoding block. This paper presents a novel Hybrid ARQ scheme which is focused on reducing the number of bits whose reliabilities are low and increasing the total sum of reliabilities of transmitted bits. Proposed Hybrid ARQ scheme achieves more performance gain when in combination with modulation level switching.

• Chip Characterization: Revealing a New Landscape to the NAND Flash Community • Leveraging large-scale flash drives: Write point per chip for parallelism • Flash Trends: Capacity: 43x, Latency: 2.6x, Bandwidth: 40% • Chip & Application Symbiosis: SLC performance in MLC parts - > 1 write point per chip - Bursts: up to 100% (89% on average) of SLC performance - Sustained: up to 95% (65% on average) performance improvement

Chip multiprocessor designs are the most common types of architectures seen in Network Processors. As the Network Processors are used to implement increasingly complicated applications, task distribution among the cores is becoming an important problem. In this paper, we propose a new task allocation scheme for such architectures. This scheme relies on the inherent modular nature of the networking applications and intelligently distributes modules among different execution cores. Additionally, we selectively replicate modules to parallelize execution of tasks having longer processing time. We have developed a technique that uses the probability distribution of the execution times of different modules in the networking applications. The proposed schemes result in resource utilization of up to 95%, 89%, and 84% on average for the processors with 2, 4, and 8 cores, respectively. The schemes are highly scalable and can improve the throughput by 6.72 times for 8 core processors, aggregated over four representative applications. The combination of selective replication of modules and variation-aware task allocation result in up to 12.5% (9.9% on average) performance improvement as compared to a scheme based on just mean processing time.

Nonvolatile memory such as magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with SRAM. 3-D integration technology using through-silicon vias enables stacking disparate memory technologies (e.g., SRAM and MRAM) together onto chip-multiprocessors (CMPs). The use of hybrid memories as an on-chip cache can take advantage of the best characteristics that each technology offers. However, the inherent high power density and heat removal limitation in 3-D integrated circuits may incur temperature-related problems. In this paper, we propose a runtime thermal management method for CMPs with the 3-D stacked hybrid SRAM/MRAM L2 cache. The proposed method combines dynamic cache management such as resource allocation, way-based power gating, and data migration with dynamic voltage and frequency scaling of processing cores in a temperature- and energy-aware manner. Experimental results show that the proposed runtime method with the 3-D stacked hybrid L2 cache offers up to 107.37% (55.28% on average) performance improvement and 88.47% (47.65% on average) energy efficiency improvement compared with existing thermal management methods with 3-D stacked SRAM-based L2 cache.

Mapping matrix operations on SIMD processors brings a large amount of data rearrangement that decrease the system performance. This paper proposes a Configurable Matrix Register File (CMRF) that supports both row-wise and column-wise accesses. The CMRF can be dynamically configured into different operating modes in which one or several sub-matrices can be accessed in parallel. Experimental results show that, compared with the traditional Vector Register File (VRF) and the MRF, the CMRF can respectively achieve about 2.21x and 1.6x average performance improvement. Compared with TMS320C64x+, our SIMD processor can achieve about 5.65x to 7.71x performance improvement by employing the CMRF.

Thermal management of DRAM memory has become a critical issue for server systems. We have done, to our best knowledge, the first study of software thermal management for memory subsystem on real machines. Two recently proposed DTM (Dynamic Thermal Management) policies have been improved and implemented in Linux OS and evaluated on two multicore servers, a Dell PowerEdge 1950 server and a customized Intel SR1500AL server testbed. The experimental results first confirm that a system-level memory DTM policy may significantly improve system performance and power efficiency, compared with existing memory bandwidth throttling scheme. A policy called DTM-ACG (Adaptive Core Gating) shows performance improvement comparable to that reported previously. The average performance improvements are 13.3% and 7.2% on the PowerEdge 1950 and the SR1500AL (vs. 16.3% from the previous simulation-based study), respectively. We also have surprising findings that reveal the weakness of the previous study: the CPU heat dissipation and its impact on DRAM memories, which were ignored, are significant factors. We have observed that the second policy, called DTM-CDVFS (Coordinated Dynamic Voltage and Frequency Scaling), has much better performance than previously reported for this reason. The average improvements are 10.8% and 15.3% on the two machines (vs. 3.4% from the previous study), respectively. It also significantly reduces the processor power by 15.5% and energy by 22.7% on average.