K-dTree based Gridless Maze Routing on Message Passing Multiprocessor Systems

It is known that single-layer obstacle-aware substrate routing is necessary for modern IC/Package designs. In this article, given a set of two-pin nets and a set of rectangular obstacles inside a single-layer routing plane, a two-phase routing algorithm including an iterative routing phase and a rip-up-and-reroute phase can be proposed to maximize the number of the routed nets in single-layer obstacle-aware substrate routing. In the iterative routing phase, based on the pin and path distribution of the routing nets and the locations of the obstacles inside a single-layer routing plane, the start or target pins on some routing nets inside dense obstacle regions may be firstly reassigned to complete the partial wiring paths on the nets. Based on the region extraction of two intersected nets in single-layer routing, the private regions of some routing nets inside sparse obstacle regions can be extracted and the nets inside the extracted regions can be further routed by using maze routing. In the rip-up-and-reroute phase, the routability of the routing nets can be improved by ripping up some routed nets and rerouting the unrouted nets. Compared with Liu's modified algorithm and Yan's flow-based algorithm in single-layer obstacle-aware substrate routing, the experimental results show that the proposed algorithm can use less CPU time to increase 3.4% and 1.8% of the routability on the routing nets for eight tested examples on the average. Additionally, the percentage of the tested examples with the 100% routability of the routing nets on the eight tested examples has been improved from 25% to 62.5%.

The development of computing systems with large numbers of processors has been motivated primarily by the need to solve large, complex problems more quickly than is possible with uniprocessor systems. Traditionally, multiprocessor systems have been uniprogrammed, i.e., dedicated to the execution of a single set of related processes, since this approach provides the fastest response for an individual program once it begins execution. However, if the goal of a multiprocessor system is to minimize average response time or to maximize throughput, then multiprogramming must be considered.In this paper, a model of a simple multiprocessor system with a two‐program workload is reviewed; the model is then applied to an Intel iPSC/2 hypercube multiprocessor with a workload consisting of parallel wavefront algorithms for solving triangular systems of linear equations. Throughputs predicted by the model are compared with throughputs obtained experimentally from an actual system. The results provide validation for the model and indicate that significant performance improvements for multiprocessor systems are possible through multiprogramming.

Multiprocessor is another great technology that helps in advancing human civilization due to high demands for solving complex problems. A multiprocessing system can have a lot of replicated processor-memory pairs (henceforth regard as net) or also called as processing nodes. Each of these nodes is connected to each other through interconnection networks and passes message using a standard message passing mechanism. In this paper, we present a routing algorithm based on enhanced simulated annealing technique to provide the connection between nodes in a semi-diagonal torus (SD-Torus) network. This network is both symmetric and regular; thus, make it very beneficial in the implementation process. The main objective is to maximize the number of established connection between nodes in this SD-Torus network. In order to achieve this objective, each node must be connected in its shortest way as possible. We start our algorithm by designing shortest path algorithm based on Dijkstra’s method. While this algorithm guarantees to find the shortest path for each single net, if it exists, each routed net will form obstacle for later paths. This increases the complexity to route later nets and makes routing longer than optimal, or sometimes impossible to complete. The solution is further refined by re-routing all nets in different orders using simulated annealing method. Through simulation program, our proposed algorithm succeeded in performing complete routing up to 81 nodes with 40 nets in 9×9 SD-Torus network size.

A Computer Aided Design (CAD) tool consisting of two new interconnect network routing algorithms is developed. It was developed to assist in manufacturing test development for any Programmable Logic Device (PLD) such as Complex Programmable Logic Devices (CPLDs) and/or Field Programmable Gate Array (FPGA) devices which utilize any interconnect network structure whose definition/connectivity and control can be described in a presented manner. The CAD tool utilizing the new routing algorithms supports manual and semiautomatic explicit, non-explicit, and net routing and was extensively tested on the interconnect networks of the Cypress Delta39K/sup TM/ series CPLD for the purpose of manufacturing testing of the programmable interconnect networks within the device as well as all programmable logic functions of the device. The two routing algorithms were developed and experimentally proved to work correctly with the best one chosen based on both theoretical and experimental complexity analysis and the particular routing scenario to be solved. The resultant routing CAD tool will produce the configuration bits necessary to program or configure PLD devices for the extensive tests that must be applied to ensure that the manufactured PLDs are defect-free. The router CAD tool can also be extensively used in the verification of the design process of PLDs as verified via experimental testing.

For the past decade, IP (Internet Protocol) routing approaches utilize TCAM (Ternary Content Addressable Memory) for the rule matching in the switches. These approaches are expensive and require more power consumption. Fortunately, the emerging of segment routing can resolve this drawback by encoding a routing path into the packet header to forward the packets to a destination. However, the standard segment routing algorithm has encountered a main problem. Using the shortest path to forward the packets can lead to a high traffic load on these paths and a performance reduction. It results in a decrease in user’s perception and some negative economic impacts for ISPs (Internet Service Providers). Therefore, in this paper, we propose a novel service-centric segment routing mechanism using reinforcement learning in the context of encrypted traffic. Our proposal aims to help ISPs to decrease the influence of the network problems and meet the strict user’s requirement related to QoE (Quality of Experience). The obtained results under the considered conditions demonstrate that our approach out-performs the standard segment routing algorithm and requires reasonable computational cost.

A comprehensive technique to plan path for a mobile robot with nonholonomic constraints through maze routing technique has been presented. Our robot uses a stereo vision based approach to detect the obstacles by creating dense 3D point clouds from the stereo images. ROS packages have been implemented on the robot for specific tasks of providing: i) Linear and angular velocity commands, ii) Calibration and rectification of the stereo images for generating point clouds, iii) Simulating the URDF (Unified Robot Description Format) module in real time, with respect to the real robot and iv) For visualizing the sensor data. For efficient path planning a hybrid technique using Lee's algorithm, modified by Hadlock and Soukup's algorithm has been implemented. Different path planning results have been shown using the maze routing algorithms. Preliminary results shows that Lee's algorithm is more time consuming in comparison with other algorithms. A hybrid of Lee's with Soukup's algorithm is more efficient but unpredictable for minimal path. A hybrid of Lee's with Hadlock's algorithm is the most efficient and least time consuming.

This paper presents a new algorithm for channel routing of multiterminal nets. We first transform any multiterminal problem of density d to a socalled extended simple channel routing problem (ESCRP ) of density 3d/2+O(√dlog d), which will then be solved with channel width w ≤3d/2+O(√dlog d) in the knock-knee model. The same strategy can be used for routing in the other two models: The channel width is w ≤ 3d/2+O(√dlog d)+O(f) in the Manhattan model, where f is the flux of the problem, and w ≤ 3d/2+O(√dlogd) in the unit-vertical-overlap model. In all three cases we improve the best known upper bounds.

This chapter describes parallel processing of robot-arm control computation and simulation. The parallel processing of robot control computation has attracted much attention to develop a cost-effective, compact, and advanced robot controller which allows a robot system to perform very complicated operations quickly and accurately even in hazardous environments, such as space and ocean floor. Also, parallel processing of robot motion simulation is important to efficiently develop the advanced robot hardwares and the controllers. This chapter introduces several parallel processing schemes on multiprocessor systems for the robot-arm control computation and the robot-arm simulation. More concretely, first of all, parallel processing schemes for the Newton-Euler equations for dynamic control are introduced. Secondly, how to implement the schemes on an actual multiprocessor system is discussed. Thirdly, parallel processing schemes for Walker & Orin’s algorithm for dynamics simulation and an implementation of the schemes on a multiprocessor system are described. Finally, future directions of the parallel processing of the robot control and simulation are briefly discussed.

Global routing is a critical stage in the VLSI design flow, aiming to provide a robust guide for detailed routing and serve as early design feedback for placement. Many approaches have leveraged GPU parallelization to achieve significant acceleration. However, with the fast-growing complexity of modern large-scale designs, recent GPU-accelerated maze routing algorithms, driven by the sweep operation, struggle to find solutions efficiently with limited GPU memory resources. In order to address this issue, this paper proposes a scalable, GPU-friendly sweep-based maze routing that requires significantly less memory and fewer kernel function calls while accelerating overall runtime. We introduce a sweep-sharing technique that allows multiple nets to be routed simultaneously within a single sweeping process, substantially reducing memory consumption and kernel launching overhead. We further propose an edge-level rip-up-andreroute technique that selectively reroutes only overflowed segments, preserving feasible parts of the solution to reduce runtime substantially. Experimental results on the latest ISPD’24 Contest benchmarks demonstrate that our GPUfriendly maze routing with sweep sharing can significantly improve the efficiency of the state-of-the-art GPU-accelerated maze router.

Intellectual properties (IPs) in design form are integrated for incremental design of system-on-chip (SoC). In order to realize proper functionality of an SoC, some global signal nets are often needed to be connected between the design IPs. If the component IPs are in-house, the global nets may be routed through the routing region of the design IPs and this routing may be formulated as an adaptive incremental routing problem where all the routing issues need to be tackled directly in the detailed routing phase only. In this work, we propose a technique for adaptive incremental routing of global nets with the objectives of minimal increase in wire length, congestion, and number of vias. The first objective maintains the desired frequency, the second and the third ones reduce the power overhead, and specifically the third one is effective in keeping the layout manufacture-friendly. The proposed technique is applied on some ISCAS’85 benchmarks and finally on a crypto SoC design which integrates several component designs for crypto-cores. The results on CPU time for routing and the overhead of routing are encouraging.

The basis of a QoS-based routing algorithm is a dynamic network dependent cost function that is used to find the optimal or at least a feasible route across the network. However, all QoS-based routing algorithms suffer from a major drawback. The cost function at the core of the algorithms identifies segments of the network where resources are ample and exploits them to the benefit of connections that would otherwise cross a congested portion of the network. Thus, the algorithms consume more resources than Minimum Hop routing would do when the network traffic is non-stationary and heavy. QoS-based routing, thus, wastes resources and performs poorly compared with Minimum Hop routing in the event of congestion. The crux of the discussion is that whatever is gained at low or medium network loads, is offset at high network loads. What is required is a resilient algorithm that either allows the migration of a QoS-based routing algorithm to a Minimum Hop algorithm at high loads or an algorithm that merges Minimum Hop and QoS characteristics. The study opts for the latter approach and proposes and exhibits a hop constrained QoS routing algorithm that outperforms traditional QoS routing algorithms during simulation. This routing technique is based on an approximation algorithm that solves the hop constrained routing problem. The algorithm is derived from a dynamic programming FPAS scheme and finds the shortest walk for a single source destination pair in a graph with restricted number of hops when all the edge costs are non-negative. Simulated results demonstrate that routing technique based on the algorithm is robust to changes in the traffic pattern and consistently outperforms other QoS based routing techniques under heavy load conditions.

본 논문은 MPI 집합 통신 함수가 처리 레벨 (transaction level) 에서 변환된다는 가정 하에 MPI 집합 통신 중 방송 (Broadcast), 확산 (Scatter), 취합 (Gather) 함수를 최적화한 알고리즘을 제안하였다. 또한 제안하는 알고리즘이 구동되는 MPI 전용 하드웨어 엔진을 설계하였으며, 이를 OCC-MPE (Optimized Collective Communication - Message Passing Engine) 라 명명하였다. OCC-MPE는 표준 송신 모드 (standard send mode)로 점대점 통신 (point-to-point communication) 을 하며, 집합 통신 중 가장 빈번하게 사용되는 방송, 취합, 확산을 제안하는 알고리즘에 의해 전송 순서를 결정한 후 통신하여 전체 통신 완료 시간을 단축시켰다. 제안한 알고리즘들의 성능을 측정하기 위하여 OCC-MPE를 SystemC 기반의 BFM(Bus Functional Model)을 제작하였다. SystemC 기반의 시뮬레이터를 통한 성능 평가 후에 VerilogHDL을 사용하여 제안하는 OCC-MPE를 포함한 MPSoC (Multi-Processor System on a Chip)를 설계하였다. TSMC 0.18 공정으로 합성한 결과 프로세싱 노드가 4개일 때 각 OCC-MPE가 차지하는 면적은 약 1978.95 이었다. 이는 전체 시스템에서 약 4.15%를 차지하므로 비교적 작은 면적을 차지함을 확인하였다. 본 논문에서 제안하는 OCC-MPE를 MPSoC에 내장하면, 비교적 작은 하드웨어 자원의 추가로 높은 성능향상을 얻을 수 있다. In this paper, on the assumption that MPI collective communication function is converted into a group of point-to-point communication functions in the transaction level, an algorithm that optimizes broadcast, scatter and gather function among MPI collective communication is proposed. The MPI hardware engine that operates the proposed algorithm was designed, and it was named the OCC-MPE (Optimized Collective Communication Message Passing Engine). The OCC-MPE operates point-to-point communication by using the standard send mode. The transmission order is arranged according to the algorithm that proposes the most frequently used broadcast, scatter and gather functions among the collective communications, so the whole communication time is reduced. To measure the performance of the proposed algorithm, the OCC-MPE with the Bus Functional Model (BFM) based on SystemC was designed. After evaluating the performance through the BFM based on SystemC, the proposed OCC-MPE is designed by using VerilogHDL. As a result of synthesizing with the TSMC <TEX>$0.18{\mu}m$</TEX>, the gate count of each OCC-MPE is approximately 1978.95 with four processing nodes. That occupies approximately 4.15% in the whole system, which means it takes up a relatively small amount. Improved performance is expected with relatively small amounts of area increase if the OCC-MPE operated by the proposed algorithm is added to the MPSoC (Multi-Processor System on a Chip).

Aiming to reduce energy consumption, minimize transmission latency, and optimize the long-term performance of Wireless Sensor Networks (WSN), this paper proposes an improved routing model of Directed Diffusion. We formulated the routing issue as a partially observable Markov decision process (POMDP), such that the optimal nodes selection policy yielded by maximizing the expected reward. Since the solution of POMDP is ready-made, the attention is concentrated only on the formulation of the routing issue into a POMDP model, more specifically, the definition of the tuple which contains states, actions, observations, transition probabilities, observation probabilities, and reward function. Our experimental study shows that the POMDP-based Directed Diffusion routing outperforms other routing techniques in terms of three widely used metrics including average dissipated energy, average delay, and average lifetime.

High-performance fault simulation is one of the essential and preliminary tasks in the process of online and offline testing of machine learning (ML) hardware. Deep neural networks (DNN), as one of the essential parts of ML programs, are widely used in many critical and non-critical applications in Systems-on-Chip and ASIC designs. Through fault simulation for DNNs, by increasing the number of neurons, the fault simulation time increases exponentially. However, the software architecture of neural networks and the lack of dependency between neurons in each inference layer provide significant opportunity for parallelism of the fault simulation time in a multi-processor platform. In this paper, a multi-thread technique for hierarchical fault simulation of neural network is proposed, targeting both permanent and transient faults. During the process of fault simulation the neurons for each inference layer will be distributed among the executing threads. Since in the process of hierarchical fault simulation, the faulty neuron demands proportionally enormous computation comparing to behavioural model of non-faulty neurons, the faulty neuron will be assigned to one thread while the rest of the neurons will be divided among the remaining threads. Experimental results confirm the time efficiency of the proposed fault simulation technique on multi-processor architectures.

Application of SLAM in the design and performance analysis of a multi-processor database system