Channel routing of multiterminal nets

Channel routing for strictly multiterminal nets

Wireless mesh networks are being deployed all around the world both to provide ubiquitous connection to the Internet and to carry data generated by several services (video surveillance, smart grids, earthquake early warning systems, etc.). In those cases where fixed power connections are not available, mesh nodes operate by harvesting ambient energy (e.g., solar or wind power) and hence they can count on a limited and time-varying amount of power to accomplish their functions. Since we consider mesh nodes equipped with multiple radios, power savings and network performance can be maximized by properly routing flows, assigning channels to radios and identifying nodes/radios that can be turned off . Thus, the problem we address is a joint channel assignment and routing problem with additional constraints on the node power consumption, which is NP-complete. In this paper, we propose a heuristic, named minimum power channel assignment and routing algorithm (MP-CARA), which is guaranteed to return a local optimum for this problem. Based on a theoretical analysis that we present in the paper, which gives an upper bound on the outage probability as a function of the constraint on power consumption, we can guarantee that the probability that a node runs out of power with MP-CARA falls below a desired threshold. The performance of MP-CARA is assessed by means of an extensive simulation study aiming to compare the solutions returned by MP-CARA to those found by other heuristics proposed in the literature.

It is known that single-layer obstacle-aware substrate routing is necessary for modern IC/Package designs. In this article, given a set of two-pin nets and a set of rectangular obstacles inside a single-layer routing plane, a two-phase routing algorithm including an iterative routing phase and a rip-up-and-reroute phase can be proposed to maximize the number of the routed nets in single-layer obstacle-aware substrate routing. In the iterative routing phase, based on the pin and path distribution of the routing nets and the locations of the obstacles inside a single-layer routing plane, the start or target pins on some routing nets inside dense obstacle regions may be firstly reassigned to complete the partial wiring paths on the nets. Based on the region extraction of two intersected nets in single-layer routing, the private regions of some routing nets inside sparse obstacle regions can be extracted and the nets inside the extracted regions can be further routed by using maze routing. In the rip-up-and-reroute phase, the routability of the routing nets can be improved by ripping up some routed nets and rerouting the unrouted nets. Compared with Liu's modified algorithm and Yan's flow-based algorithm in single-layer obstacle-aware substrate routing, the experimental results show that the proposed algorithm can use less CPU time to increase 3.4% and 1.8% of the routability on the routing nets for eight tested examples on the average. Additionally, the percentage of the tested examples with the 100% routability of the routing nets on the eight tested examples has been improved from 25% to 62.5%.

An important part of the integrated circuit design process is the channel routing stage, which determines how to interconnect components that are arranged in sets of rows. The channel routing problem has been shown to be NP-complete, thus this problem is often solved using genetic algorithms. The traditional objective for most channel routers is to minimize total area required to complete routing. However, another important objective is to minimize signal propagation delays in the circuit. This paper describes the development of a genetic channel routing algorithm that uses a Pareto-optimal approach to accommodate both objectives. When compared to the traditional channel routing approach, the new channel router produced layouts with decreased signal delay, while still minimizing routing area.

An efficient merger of the channel routing theory and the genetic stochastic search introduces a new paradigm for VLSI channel routing. The feasibility of the paradigm is demonstrated by the first genetic router for Manhattan model channels which contain cyclic vertical constraints. The router has been implemented as a self contained genetic algorithm system. It creates an initial population without violations of constraints using the results of a new theory of locally optimal breaking of cyclic vertical constraints. The population size is problem instance dependent to provide for the preservation of the structural diversity which is built into the initial population. A new encoding scheme and novel crossover and mutation operators are introduced. Convergence rates to optimal solutions are excellent.

In this paper we have developed algorithms for generating random channel instances for their use in computing channel routing solutions in VLSI physical design. Channel instances are usually of two types: simple and general, and there are usually two kinds of inherent constraints involving channel routing problem: horizontal constraint and vertical constraint. Simple channel instances do not contain any vertical constraint, whereas, general channel instances contain both horizontal as well as vertical constraints. Most of the optimization problems in two-, three-, and multi-layer channel routing are NP-hard and, in fact, very few are polynomial time computable. Hence for each of the NP-hard problems in channel routing, it is unlikely to design a polynomial time deterministic algorithm. Developing heuristic algorithm may be a probable way out that hopefully provides good solutions for most of the instances available in literature. Novelty of a heuristic algorithm is judged better if it works for a variety of large number of randomly generated instances of the problem.

A Computer Aided Design (CAD) tool consisting of two new interconnect network routing algorithms is developed. It was developed to assist in manufacturing test development for any Programmable Logic Device (PLD) such as Complex Programmable Logic Devices (CPLDs) and/or Field Programmable Gate Array (FPGA) devices which utilize any interconnect network structure whose definition/connectivity and control can be described in a presented manner. The CAD tool utilizing the new routing algorithms supports manual and semiautomatic explicit, non-explicit, and net routing and was extensively tested on the interconnect networks of the Cypress Delta39K/sup TM/ series CPLD for the purpose of manufacturing testing of the programmable interconnect networks within the device as well as all programmable logic functions of the device. The two routing algorithms were developed and experimentally proved to work correctly with the best one chosen based on both theoretical and experimental complexity analysis and the particular routing scenario to be solved. The resultant routing CAD tool will produce the configuration bits necessary to program or configure PLD devices for the extensive tests that must be applied to ensure that the manufactured PLDs are defect-free. The router CAD tool can also be extensively used in the verification of the design process of PLDs as verified via experimental testing.

Routing in times square mode

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this paper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonal model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

A new algorithm for channel routing is presented which addresses the special problems of bit-slice architectural assembly, namely the broadcasting and cascading of signals through layout slices. This is achieved by end-on abutment of channels. The method, used in the bit-slice assembler Slicesyn, is based on a heuristic approach using graph theory.

The routing of nets or a set of interconnection points is a compute intensive application encountered in CAD for VLSI design. In this paper, we propose a gridless algorithm for area routing based on the Hightower's Maze routing algorithm for message passing multiprocessor systems. The suitability of k-d trees as a data structuring technique for gridless maze routing is established. Since segments of routes are stored as rectangular objects in the k-d tree, the algorithm facilitates routing with variable width conductor paths. Results obtained both through simulation techniques and those obtained on an actual multiprocessor system based on message passing exhibit speedup proportional to the number of processors in the multiprocessor system.

A new channel routing model, which allows horizontal and vertical wire segments to be placed on both layers and two wires on different layers to be overlapped, is presented. Based on this model, the basic constraints as well as the rules of layer assignment and routing order in two-layer channel routing are obtained. Then the property of optimal overlapping in a zone is analyzed. For the example used, this algorithm obtains 18 tracks solution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The authors present a new three-layer over-the-cell channel routing algorithm, WILMA3 (wire length minimization algorithm 3), for high-performance circuits. This router not only minimizes the channel height by OTC routing but also minimizes the net lengths. They have also developed a two-layer router, WILMA2. Both WILMA2 and WILMA3 achieve reduction in channel height while maintaining the net length greater than its length in the two-layer channel routing. Experimental results with WILMA2 indicated that WILMA2 can produce routings that are comparable to existing two-layer over-the-cell routers. Both WILMA2 and WILMA3 achieved these results, while maintaining the net length bound. >

We present a new cell model for over-the-cell routing and a new over-the cell multi-channel routing method. In the proposed new cell model, terminals can be placed arbitrarily on the second layer of a cell so that each cell does not require the extra routing region on the first layer of a cell to align terminals. Unlike conventional cell models, some parts of the second layer are also utilized for the intra-cell routing in order to reduce the chip area. Therefore the size of the proposed cell model can be smaller than that of a conventional cell model. The proposed method consists of three phases. In order to utilize the proposed cell model, in phase 1, we simultaneously handle all channels to determine the most effective routing patterns from the set of possible routing patterns to minimize the chip area. In phase 2, for the effective routing patterns of nets selected in phase 1, over-the-cell routing nets are selected by a new greedy algorithm considering obstacles on over-the-cells. Finally, the conventional channel routing algorithm is applied for nets unrouted on over-the-cell. From the experimental results with MCNC benchmarks, the proposed cell model and algorithm produce smaller height of layouts as compared to those produced by conventional cell models and algorithms, and the effectiveness of the proposed method and cell model was shown.

Necessary and sufficient conditions for the routability of classical channels