Over-the-cell channel routing for high performance circuits

Channel routing and crosstalk minimization are important issues while we talk about high-performance circuits for VLSI physical design automation. Interconnection among the net terminals satisfying constraints in an intelligent way is a necessity to realize a circuit in a minimum possible area, as this is a primary requirement to reduce cost as well as to increase yield. In this paper, along with area minimization, the performance of the computed circuits has also been enhanced by computing routing solutions with a specified amount of bottleneck crosstalk in two-layer channel routing. Usually, crosstalk is measured by the amount of overlapping of a pair of nets assigned to adjacent tracks. The crosstalk minimization problem in the reserved two-layer Manhattan channel routing model is NP-hard. Thus, in this paper, heuristic algorithms have been devised to optimize bottleneck crosstalk in order to augment circuit performance in two-layer channel routing. Experimental results obtained are highly encouraging.

A new channel routing model, which allows horizontal and vertical wire segments to be placed on both layers and two wires on different layers to be overlapped, is presented. Based on this model, the basic constraints as well as the rules of layer assignment and routing order in two-layer channel routing are obtained. Then the property of optimal overlapping in a zone is analyzed. For the example used, this algorithm obtains 18 tracks solution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Wireless mesh networks are being deployed all around the world both to provide ubiquitous connection to the Internet and to carry data generated by several services (video surveillance, smart grids, earthquake early warning systems, etc.). In those cases where fixed power connections are not available, mesh nodes operate by harvesting ambient energy (e.g., solar or wind power) and hence they can count on a limited and time-varying amount of power to accomplish their functions. Since we consider mesh nodes equipped with multiple radios, power savings and network performance can be maximized by properly routing flows, assigning channels to radios and identifying nodes/radios that can be turned off . Thus, the problem we address is a joint channel assignment and routing problem with additional constraints on the node power consumption, which is NP-complete. In this paper, we propose a heuristic, named minimum power channel assignment and routing algorithm (MP-CARA), which is guaranteed to return a local optimum for this problem. Based on a theoretical analysis that we present in the paper, which gives an upper bound on the outage probability as a function of the constraint on power consumption, we can guarantee that the probability that a node runs out of power with MP-CARA falls below a desired threshold. The performance of MP-CARA is assessed by means of an extensive simulation study aiming to compare the solutions returned by MP-CARA to those found by other heuristics proposed in the literature.

A new algorithm for channel routing is presented which addresses the special problems of bit-slice architectural assembly, namely the broadcasting and cascading of signals through layout slices. This is achieved by end-on abutment of channels. The method, used in the bit-slice assembler Slicesyn, is based on a heuristic approach using graph theory.

An efficient merger of the channel routing theory and the genetic stochastic search introduces a new paradigm for VLSI channel routing. The feasibility of the paradigm is demonstrated by the first genetic router for Manhattan model channels which contain cyclic vertical constraints. The router has been implemented as a self contained genetic algorithm system. It creates an initial population without violations of constraints using the results of a new theory of locally optimal breaking of cyclic vertical constraints. The population size is problem instance dependent to provide for the preservation of the structural diversity which is built into the initial population. A new encoding scheme and novel crossover and mutation operators are introduced. Convergence rates to optimal solutions are excellent.

With recent advances in vertical-integration technology, it is now reasonable to consider a three-dimensional IC structure containing either partially or completely stacked active layers. Thus it is possible to have stacked terminals at the channel edges. In this case, each terminal is constrained to a specific layer and therefore may only enter the channel on the layer to which it is constrained. For a channel of length λ using n layers for routing, it is now possible to have 2nλ terminals on the edges of the channel. A new channel-routing algorithm is presented for routing channels consisting of stacked and constrained terminals. The algorithm employs greedy heuristics, routing the channel column by column from left to right. The router guarantees a solution, although one or more extra columns off the end of the channel may be required. The heuristics of the router can be easily modified to rearrange priorities or to add new requirements or constraints. The algorithm has been tested extensively using randomly-generated channel descriptions. Very good solutions were obtained in a short amount of CPU time.

In the channel routing problem, a problem arising in the design of layout systems, two rows of terminals which are opposite each other, have to be connected. We study what effect the rotation of one row of terminals has on the cost measures of the routing phase. The cost measures we consider are the density, which is proportional to the width of the channel, the crossing number, which is closely related to the number of crossings between two wires in the channel, and the length of nets, which is related to the wire length needed in the routing. We present algorithms for determining the rotations which minimize each of these cost measures. The algorithms can also be used for solving optimal offset problems.

As technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction of crosstalk between interconnection wires becomes an important consideration in VLSI design. In this paper, we study the gridded channel routing problem with tbe objective of satisfying crosstalk constraints for the nets. We proposed a new approach to the problem which utilizes existing channel routing algorithms and improves upon the routing results by permuting the routing tracks. The permutation problem is proven to be NP-complete. A novel mixed ILP formulation and effective procedures for reducing the number of variables and constraints in the mixed ILP formulation are then presented. The new algorithm is tested on three large benchmark circuits as well as many randomly generated circuits. The experimental results are very promising.

Channel routing problem of area minimization is a well-defined problem in VLSI physical design automation. In this paper we have developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions. Here we consider the total wire length of a routing solution as one of the most important factors of high performance computing. Reduction in wire length is important from signal delay as well as from the viewpoint of cost of wire segments required in interconnecting all the nets. The framework is designed for computing routing solutions in two-layer channels, and extended to route three-layer routing also in a modular fashion. All the algorithms developed under the framework of TAH are executed for computing no-dogleg and dogleg routing solutions for most of the well-known benchmark channels, with reduced total area and/or total wire length in two- and three-layer channel routing. Performance of our algorithms is highly encouraging.

An important part of the integrated circuit design process is the channel routing stage, which determines how to interconnect components that are arranged in sets of rows. The channel routing problem has been shown to be NP-complete, thus this problem is often solved using genetic algorithms. The traditional objective for most channel routers is to minimize total area required to complete routing. However, another important objective is to minimize signal propagation delays in the circuit. This paper describes the development of a genetic channel routing algorithm that uses a Pareto-optimal approach to accommodate both objectives. When compared to the traditional channel routing approach, the new channel router produced layouts with decreased signal delay, while still minimizing routing area.

The goal of a channel routing algorithm is to route the nets with as few tracks as possible to minimize the chip area and achieve 100 percent connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce the critical areas which are susceptible to defects. A new channel routing algorithm is presented to deal with this problem. The approach is to systematically eliminate critical areas by floating, burying, and bumping net segments as well as shifting vias. The yield optimizing routing (YOR) algorithm also minimizes the number of vias. The experimental results show that large reduction in the number of critical areas and significant improvement in yield are achieved. >

Spectrum-aware cross-layered routing protocol for cognitive radio ad hoc networks

Adiabatic quantum-flux-parametron (AQFP) logic is a very energy-efficient superconductor logic due to zero static power dissipation and adiabatic switching operation. However, there is a shortage of electronic design automation (EDA) software tools adaptable to AQFP logic. Such tools are essential for designing large-scale-integration circuits efficiently. Therefore, we have developed a first set of EDA tools that handle cell placement and wiring, written in SKILL, the Cadence scripting language. Our tools also consider the maximum wire length constraint that exists in AQFP logic. First, AQFP logic cells are repositioned via the genetic algorithm to minimize the number of wires that violate the wiring length constraint. Buffers are then automatically inserted as signal repeaters for logic rows where the violations still exist. We then complete the logic wiring of the circuit using the channel routing algorithm. We demonstrate the usability of the EDA tools by designing a 16-bit adder as well as a randomly generated test circuit.

In this paper, visualization techniques are applied to the implementation and analysis of a known channel routing algorithm. The main features of the algorithm are visualized in order to make easier the user's approach to it.

This paper presents a new algorithm for channel routing of multiterminal nets. We first transform any multiterminal problem of density d to a socalled extended simple channel routing problem (ESCRP ) of density 3d/2+O(√dlog d), which will then be solved with channel width w ≤3d/2+O(√dlog d) in the knock-knee model. The same strategy can be used for routing in the other two models: The channel width is w ≤ 3d/2+O(√dlog d)+O(f) in the Manhattan model, where f is the flux of the problem, and w ≤ 3d/2+O(√dlogd) in the unit-vertical-overlap model. In all three cases we improve the best known upper bounds.