Lowinput voltage charge pump with dynamic body biasing

This paper proposes a low input voltage charge pump using 0.18um CMOS process for energy harvesting. There are two main sections in the charge pump system: Low Voltage Charge Pump (LVCP) and High Voltage Charge Pump (HVCP). In the LVCP, a negative charge pump is utilized to improve the efficiency at low input voltage, Dynamic Body Bias (DBB) and switch-conductance enhancement techniques are applied to a unit stage of the two-stage charge pump. In the HVCP, the charge pump circuit utilizes charger transfer switches (CTS) with a complementary banch scheme to significantly reduce undesired charge transfer, and an optimized gate control strategy is applied to further decrease the power loss caused by undesired charge transfer. The simulation result demonstrates that the proposed circuit can achieve 97% voltage conversion and drive 800uA load current at 0.6V input voltage. In the region of 0.4V to 0.6V input voltage, the circuit performs well with the load resistance of 10K ohms.

Design of low-voltage and efficient energy-harvesting circuits is becoming increasingly important, particularly, for autonomous systems. Since the amount of energy that can be harvested from the surrounding environment is limited, the available output voltage of a harvester is low. Therefore, the design of a low-input-voltage (low-VIN) up-converter is critical to self-powered systems [1-3]. Moreover, the form factor is very constrained in applications such as wearable electronic devices and sensor networks. Recently, low-VIN charge pumps (CPs) for energy harvesting has been compared with DC-DC converters using a large inductor [1-3]. CPs introduced in [1] and [2] use the advanced process technology to push VIN down to the subthreshold region. The CP in [1] introduces a forward-body-biasing (FBB) technique, which improves the voltage conversion efficiency (VCE) for low VIN but shows poor power conversion efficiency (PCE). The CP in [2] achieves the lowest operation voltage. However, the design with a 10-stage CP provides low output power. This paper presents a CP with switching-body-biasing (SBB), adaptive-dead-time (AD), and switch-conductance (SW-G) enhancement techniques to improve the PCE for low VIN as well as to extend the maximum load current.

Based on the magnetic coupling resonant wireless power transmission technology, how to improve the efficiency of the system under the condition of low voltage and high current input is studied. In this paper, a wireless power transfer system based on Z-source inverter is proposed. In the environment of low voltage and high current input, the input voltage is low, and the increase of DC-DC link will increase the loss of the system. Therefore, this paper analyzes the circuit of the magnetically coupled resonant wireless power transmission system in the low-voltage input and high-current output environment, and applies the Z-source inverter to the low-voltage and high-current input environment to improve the performance of the system.

In this paper, a low‐voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross‐connected NMOS voltage doubler stages. For very low‐voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD‐PMOS) in parallel to the cross‐connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD‐BCLK). Simulations at 50 MHz have shown that a five‐stages charge pump with CVD can achieve a 1.5–8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD‐PMOS and the charge pump with CVD‐BCLK, respectively.

New SOI processes offer unprecedented flexibility in regard to low-power and performance. The use of fine-grained body biasing in STMicro's 28nm UTBB-FDSOI is evaluated for a Dynamically Reconfigurable Processor design in a frequency scaling scenario. Three different strategies are evaluated for Processing Elements: Static, programmable and dynamic body biasing. Fine-grained body biasing significantly mitigates increased leakage currents of forward body biasing between 42.85% to 64.5% on average. This makes static body biasing a viable low-cost option and makes dynamic body biasing worthwhile even at short time periods.

This paper presents the design of a digital controller for a 600 W Boundary-Conduction-Mode (BCM) interleaved boost converter used in an ac-dc Power-Factor-Correction (PFC) power supply. The output voltage of a typical boost PFC rectifier contains a 2nd harmonic ripple. Therefore to achieve good power factor, the output voltage compensator must have a low bandwidth, in order to sufficiently attenuate this 2nd harmonic component. As a result, the output voltage can suffer from poor transient response, especially at low input voltage. In this paper, a small-signal model of the output voltage dynamics is derived, where it is shown the open-loop gain of the system decreases with low input voltage. As a result, the output voltage transient response also deteriorates at low levels of input voltage. This can lead to poor voltage transient response for boost PFC converters that are designed to have an operating input line voltage range from 85 to 265 V. Having poor output voltage transient response is undesirable as it can lead to high peak over shoot on the output capacitors, or even worse, lead to an output voltage tracking failure. To correct this behaviour, an adaptive digital voltage compensator is designed to change gain at low input voltage, to ensure the output voltage maintains good transient response. Finally, the derived small-signal analysis, and output voltage compensator performance are experimentally verified on a 600 W interleaved BCM converter.

This paper proposes a new organization of charge pump circuits based on a voltage doubler that takes a DC input and outputs a doubled DC voltage. By cascading n multi-phase voltage doublers (MPVD), the resulting charge pump has the voltage gain equal to 2/sup n/. It needs n clock pairs to control the pumping process, MPVD is a minimum capacitance realization of the switched-capacitor based voltage doubler. An n-stage MPVD needs n+1 capacitors and 2/sup n/ switches. To avoid the short circuit during switching, a dock pairs generator is used to achieve multi-phase non-overlapping clock pairs. A frequency regulator is designed to lower the charging frequency when the load becomes lighter, thus reducing the power loss during switching. A 2-stage MPVD is implemented in the Orbit 2.0 /spl mu/m analog CMOS technology. The simulation results show that the output voltage is 3.995 times the power supply. By using the frequency regulator, the power efficiency is dramatically improved when the load becomes lighter.

This letter presents a millimeter-wave (mm-wave) two-stage rectifier. It is designed to power a backscattering low voltage RFID tag system providing the maximum power conversion efficiency (PCE) at low output voltages. It utilizes the internal voltage cancellation (IVC) scheme as well as forward body-biasing (BB) for internal MOS transistors' threshold compensation. A low voltage charge pump is used to generate the differential body bias voltages. An oscillator with regulated power supply is designed to provide a clock signal to the charge pump at very low voltages. It provides 9% PCE at -13-dBm input power and 33- kΩ equivalent loading. It has also -13-dBm sensitivity for 1-V output voltage for the open load condition.

In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Working with power supplies less than 1volt, the proposed circuit provides output impedance greater than LVC current mirror. Such outstanding features of this current mirror as high output impedance~25.3M, low input impedance~44, wide bandwidth~498 MHz, low input voltage ~ 415 mV, low output voltage ~ 149 mV and low current transfer error ~1.3% (all at 10 ¿A) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35 ¿m CMOS technology with Hspice are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror/NIC.

An interleaved high-step-up current sharing DC–DC converter with coupled inductors is proposed in this paper. The operation principle and property of this converter are analyzed. The ripple of the input current in the proposed converter is decreased significantly by using the two-phase parallel interleaved input. The voltage gain is extended and the switch voltage stress is reduced by the coupled inductors. The leakage inductance of the coupled inductors reduces the reverse-recovery problem of the output diode, resulting in the reduction of reverse-recovery losses. As there are two interleaved phases in the proposed converter, the third winding of each coupled inductor is embedded in another phase. With this design, when the leakage inductance or duty cycle is asymmetrical, the current sharing performance is still positive. Consequently, the new topology is very suitable for applications to occasions with low voltage input and high voltage output, such as the fuel cell power system. Finally, the performance of this topological circuit is verified by a prototype with 500 W output.

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. With the switching substrate technique and boosted transistor, the influence of body effect is almost eliminated and the voltage gain at each pumping node is greatly increased. So higher output voltage and higher efficiency than the conventional charge pump can be obtained by the proposed charge pump. Simulation results of different supply voltages and stage numbers at 2MHz input clock frequency are shown in this paper

An operation of electronic equipment is dependent on a power supply. Today, a trend of only one AC/DC adapter is used for supplying an electronic system. Thus, an electronic equipment with various power supply requirements uses some internal DC/DC converters. These DC/DC converters adjust input voltage to lower or/and higher value or generate a negative voltage. The classical DC/DC converters are based on inductors or transformers. These converters are too large and suitable for a higher output power. A charge pumps are a sufficient alternative to classical DC/DC converters for a lower output power and a smaller dimension. A well-known variant of a charge pump is Dickson charge pump. The output to input voltage ratio is a directly proportional to the number of Dickson charge pump stages. Thus, the number of stages can be a relatively high for low input voltage and required high output voltage. The Fibonacci charge pump is a suitable alternative to Dickson charge pump especially for a higher output to input voltage ratio. This article describes practical circuit solution of the Fibonacci charge pump. The key properties of the Dickson and the Fibonacci pumps are compared in this article, too.

Switched‐capacitor networks have been used as bandgap references (BGRs) to replace the area‐consuming resistors in ultra‐low power applications, incorporated with voltage doubler (2X) charge pumps to operate at low supply voltages. However, the open‐loop charge pumps are sensitive to supply and load variations. Therefore, in this work, constant bias currents are added to the cross‐coupled 2X charge pumps to reduce the supply sensitivity, and also to reduce the output ripples without using large capacitors. To further reduce the power consumption, a low‐leakage sample and hold (S&H) circuit is used for an intermittent operation, the active/idle duty ratio of the BGR core is 1/15. Designed in standard 65 nm CMOS, the proposed BGR reaches a temperature coefficient of 64 ppm/°C consuming only 5.4 nW with a minimum supply of 0.45 V (simulated).

With recent advancements in thermoelectric material performance, thermoelectric generators have become a viable alternative for power generation using small temperature differentials with benefits that can not be found in other energy conversion methods. The power generated by a thermoelectric generator, using a small /spl Delta/T, is characterized by a relatively high current (-/spl sim/5 A), but a relatively low voltage (<0.3 V), which is often not suited for many practical applications. In order to make use of the thermoelectric generated power in applications requiring a higher voltage, a DC-DC step up converter that can handle low input voltage is needed. Commercial available DC step up converters require an input voltage of at least 0.7 volts, which is the minimal voltage required for operating a bipolar junction switch. Several novel approaches for low input voltage DC-DC converter concepts have been studied and proved to be feasible. Their operations are based on some unconventional methods achieving DC to AC conversion for low input voltage. In one solid state approach, a normally-on transistor and a tunnel diode were utilized to achieve low voltage oscillation. A conversion concept was also developed which is based on an electromagnetic actuated mechanical switch. Operating principles and measured performance of these approaches will be reported.

In this paper, a high performance boost converter consisting of an integrated dual-boost converter and a voltage doubler is proposed. The converter possesses quadric voltage gain through single switch and the voltage doubler further increases the voltage gain as the turn ratio rises. The voltage stresses on the switch and diodes are decreased for such cascaded topology. Mathematical analysis of the converter characteristics and design method are presented in detail. The leakage inductances contribute to realizing zero current switching (ZCS) of the diodes in the second boost stage and the doubler and the energy are recycled to the load. Experiments on the 38W prototype are conducted, which verify the advantages of the proposed converter and the upmost efficiency of the system is 92%.