Non-Cutting Dynamic Power Consumption and Vibration Characterization of a Custom Built Tabletop CNC Machine with a DC Spindle Motor

The accurate modeling of the piezoelectric actuator (PEA) is fundamental to guarantee the rapidity and accuracy of positioning control for micro-nano manipulation. Nevertheless, the high-accuracy modeling of input voltage and driving displacement is difficult because the PEA has creep, vibration dynamics, nonlinear hysteresis, and system uncertainty. In this article, a compensatory nonlinear–linear–linear Hammerstein (CNLLH) modeling strategy considering creep, vibration dynamics, hysteretic nonlinearity, and uncertainty compensation for piezoelectric system is proposed to achieve an accurate input-output model for control design, where the input is voltage signal and the output is driving displacement. This model structure is a nonlinear–linear–linear-nonlinear block, where the first nonlinear model is used to describe hysteretic nonlinear behavior, the two linear models are used to describe creep and vibration characteristics, and the second nonlinear model with a neural network is used to compensate the system uncertainty. The corresponding CNLLH model identification algorithm is developed based on the singular value decomposition, regularized least-squares method, and gradient descent method. The proposed CNLLH strategy can realize the simultaneous identification of four different characteristics only based on a set of experimental data without the decoupled experiment design. Experiments are conducted on the piezoelectric system to show the correctness of the proposed CNLLH strategy.

In todaypsilas technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.

A fully power aware globally asynchronous locally synchronous network-on-chip circuit is presented in this paper. The circuit is arranged around an asynchronous network-on-chip providing a 17 Gbits/s throughput and automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each NoC units. The dynamic power consumption can be reduced up to a factor of 8 while the static power consumption is reduced by 2 decades in stand-by mode.

With the rapid evolution of network speed from 1Gbps to 10Gbps, a wide spectrum of research has been done on TCP/IP to improve its processing efficiency on general purpose processors. However, most of them did studies only from the performance perspective and ignored its power efficiency. As power has become a major concern in data centers, where servers are often interconnected with 10GbE, it becomes critical to understand power efficiency of TCP/IP packet processing over 10GbE. In this paper, we extensively examine power consumption of TCP/IP packet processing over 10GbE on Intel Nehalem platforms across a range of I/O sizes by using a power analyzer. In order to understand the power consumption, we use an external Data Acquisition System (DAQ) to obtain a breakdown of power consumption for individual hardware components such as CPU, memory and NIC etc. In addition, as integrated NIC architectures are gaining more attention in high-end servers, we also study power consumption of TCP/IP packet processing on an integrated NIC by using a Sun Niagara 2 processor with two integrated 10GbE NICs. We carefully compare the power efficiency of using an integrated NIC with using a PCI-E based discrete NIC. We make many new observations as follows: 1) Unlike 1GbE NICs, 10GbE NICs have high idle power dissipation, and TCP/IP packet processing over 10GbE consumes significant dynamic power. 2) Our power breakdown reveals that CPU is the major source of the dynamic power consumption, followed by memory. As the I/O size increases, the CPU power consumption reduces but the memory power consumption grows. Compared to CPU and memory, NIC has low dynamic power consumption. 3) Large I/O sizes are much more power efficient than small I/O sizes. 4) While integrating a 10GbE NIC slightly increases CPU power consumption, it not only reduces system idle power dissipation due to elimination of PCI-E interface in NICs, but also achieves dynamic power savings due to better processing efficiency. Our studies motivate us to design a more power efficient server architecture, which can be used in the next generation data centers.

The dynamic response and active vibration control of flexible composite material barrel under moving projectile are studied in this paper. After analyzing its vibration characteristics, the active vibration control technology is introduced to suppress its vibration. Combining theoretical modeling and experimental developing, some key problems of applying the active vibration control technology to vibration control of flexible composite barrel are discussed, which provides the technology foundation for later developing of flexible smart composite barrel. The coupling vibration model between the moving projectile and flexible composite barrel is established and solved by applying numerical iterative method and simulation experimental study, and many valuable conclusions are made. Besides, the dynamic response model and state space model for active vibration control of barrel under a moving projectile is established. And the adaptive fuzzy control strategy is introduced to suppress the flexible composite material barrel vibration. The testing system of dynamic response and active vibration control for barrel under a moving projectile is designed and developed. The experimental results showed the effectiveness of this kind of control strategy for flexible composite material barrel bonded with piezoelectric self-sensing actuator under a moving projectile, which demonstrated that using the smart material could suppress the time-varying system flexible structure vibration active control.

Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique to reduce both static and dynamic power consumption in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current during the scan shift process, and this vector can also be used to reduce dynamic power. However, the reverse is not always true. A heuristic algorithm is presented to find such vectors. The proposed method is simulated by SPICE with BPTM 22nm transistor model, and the results show that on the average 15% total power reduction is achievable by the proposed method.

SummaryHerein, by a case study on a 5‐MW wind turbine system developed by Nanjing University of Aeronautics and Astronautics, the wind field simulation and wind‐induced vibration characteristics of wind turbine tower‐blade coupled systems is analyzed. First, the blade‐nacelle‐tower‐basis integrated finite element model with centrifugal forces induced by rotational blades is established. Then, based on a harmony superposition method and the modified blade element‐momentum theory, the fluctuating wind field of tower‐blade coupled systems is simulated, which considers wind shear effect, tower shadow effect, rotational effect, blade‐tower dynamic and model interaction effects. Finally, the wind‐induced dynamic responses and wind vibration coefficients of the wind turbine tower‐blade coupled structure are discussed through the ‘consistent coupled method’ previously proposed by us. The results indicate that the wind‐induced responses of a large wind turbine tower‐blade coupled structure present complicated modal responses and multimode coupling effect. Additionally, the rotational effect would amplify aerodynamic loads on blades with high frequency, wind‐induced dynamic responses and wind vibration coefficients of wind turbine tower. The centrifugal force effect could also amplify natural vibration frequency of the tower‐blade coupled system and reduce the wind‐induced dynamic responses and wind vibration coefficients of wind turbine tower. The research could contribute to wind‐resistant design of structure for a large‐scale wind turbine tower‐blade system. Copyright © 2014 John Wiley & Sons, Ltd.

One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in system design including HW and SW, SoC architecture and logic design. Dynamic power consumption is the major factor of energy consumption in the current CMOS digital circuits. The dynamic power consumption is affected by supply voltage, load capacitance and switching activity. We present approaches to controlling supply voltage, load capacitance and switching activity dynamically and statically in system architecture and algorithm design levels. We also discuss about the memory architecture for reducing power and energy in HW and SW co-design of SoC. In the future CMOS technology, leakage power consumption becomes dominant, because the threshold voltages are scaled as the transistor size shrinks. We summarize the techniques for reducing leakage power in system architecture design. The contents of the chapter include the following issues; (1) power and energy consumptions in SoC design, (2) tradeoff between energy and performance, (3) tradeoff among energy, QoS (i.e., latency and computational precision), reliability, and flexibility (4) techniques for reducing dynamic power consumption, and (5) leakage power reduction techniques

Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. In fact, many values rarely need the full-bit dynamic range supported by a cache. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. It is unreasonable that the storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes a Variable Bitline Data Cache (VBDC) which exploits the popularity of NWV stored in the cache. In VBDC design, the cache data array is divided into several sub-arrays to adapt each data pattern with the different bitline length to access. The VBDC can shut off the corresponding unused high arrays to reduce its dynamic and static power consumption. The VBDC achieves low power consumption through reducing the bitline length. Experimental results employing SPEC 2000 benchmarks show that our proposed VBDC can reduce both the dynamic power consumption ant the static power consumption by 44.75% and 42.86%.

Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply voltage of some computational elements in the circuit, with the penalty of an increase of their execution delay. To reduce the dynamic power consumption, without degrading the performance determined assuming that the circuit operates at the highest available supply voltage, the supply voltage of computational elements off critical paths can be scaled down. Defined here as MinP/sub dyn/, the problem of minimizing the dynamic power consumption, under performance constraints, by scaling down the supply voltage of computational elements on non-critical paths is NP-hard in general. Solving MinP/sub dyn/ for multi-phase clocked sequential circuits may allow to reduce their power consumption and the required number of registers. Reducing the number of registers also allows to reduce the power consumption, the number of control signals, and the area of the circuit. In this paper, we focus on devising methods to efficiently solve MinP/sub dyn/ for designs modeled as cyclic or acyclic graphs. More precisely, once the circuit is optimized for timing constraints, then we look for schedules that allow the computational elements of the circuit to operate at the lowest possible supply voltage. We present an integer linear programming formulation for that problem, which we use to devise a polynomial time solvable method and an exact algorithm based on a branch-and-bound technique. Experimental results confirm the effectiveness of the method and power reduction factors as high as 53.84% were obtained. Also, they show that the exact algorithm produces optimal results in a small number of tries, which is due to the rules used to prune useless solutions.

In this paper we have developed a new scheduling algorithm that provides a decrease in dynamic power consumption through achieving components scheduling. The major idea of that algorithm is to amplify the latency of some components whenever it is feasible without negatively influencing the dependency constraints. For that purpose, we have decreased the frequency of the components clocks. Since frequency and power are inter-related, a decrease in frequency value will be followed by a decrease in power consumption. Our algorithm has been tested and has given an interesting gain in dynamic power.

Achieving energy efficiency is of paramount importance in facilitating the deployment of artificial intelligence (AI) applications, particularly for edge devices. The computational complexity and memory requirement of AI workloads have made energy efficiency in circuits the primary design constraint, prompting a need for architectural reconsideration. However, operations in Convolutional Neural Networks (CNN) relying on matrix multiplication offer opportunities for algorithm-level optimization. The dynamic power consumption in CMOS technology exhibits a direct correlation with the switching activities (SA) associated with transitions of data bits from one cycle to the next. Minimizing SA constitutes an effective approach to curbing power consumption, resulting in prolonged battery life. This work introduces a cross-layer end-to-end optimization technique, which involves a one-time sorting of pre-trained model parameters to reduce switching activity during matrix multiplication or convolution operations while eliminating the indexing overhead during inference. While upto 40% reduction in switching activities through sorting has been achieved, the actual saving in dynamic power achievable for the input stationary systolic array is approximately 10% in total power consumption and around 15% in switching power. The proposed method has been validated using various pre-trained networks, including GoogeLeNet, MobileNet, AlexNet, and SqueezeNet, among others.

Cryptographic systems can potentially suffer from various attacks which are a consequence of vulnearability of side channel information to analysis attacks. The nature of digital circuits is prone to electromagnetic and power analysis (EMA and PA) attacks. Interconnects in cryptographic circuits emanate information through electromagnetic signals which can be exploited using EMA. Complementary Metal Oxide Semiconductor (CMOS) circuits are vulnearable to leak of computational information through leakage and dynamic power consumption. Dynamic power consumption of cryptographic engines is a rich source to sink in the data under process. The hardware implementation of cryptographic algorithms undermine the security of encrypted system against non brute-force-attacks. The attackers collect and analyse the leakage information of cryptographic circuits to detect the secrete key. The parameters sensitivity of the device and circuits make the cryptographic engines vulnearable to fault injection and inherent inconsistency of the circuits. Dynamic and static power comprise two major components of power consumption of digital circuits. Both power components vary with data under process. This exhibits power consumption has data dependency in digital circuits. To make noisy power profile, various countermeasures have been proposed against Differential Power Analysis (DPA) attacks. In this research, false glitch cells is proposed to work as a countermeasure to generate random transitions and power spikes to scramble power profile. The mathematical foundation of security implications of false glitch cells against Correlation Power Analysis (CPA) attacks is investigated. Moreoever, the security efficiency of utilizing false glitch cells is verified with different metrics.

This paper presents an analytical dynamic power model of CMOS gates driving transmission lines with distributed RLC parameters. It is shown that at high signal frequency, where the output voltage at the termination of a transmission line may not reach the steady state during a signal period, the charge and voltage at the end of the period become the initial conditions of the following periods and have a significant effect on dynamic power consumption. The proposed model takes these initial conditions into account, since it is based on Fourier series analysis. In this model, the dynamic power consumption is approximated by the summation of the first several Fourier-series-based terms. The accuracy of the model increases with the number of series terms, and arbitrary accuracy can be obtained by including appropriate number of the terms in the model. The model is much faster than simulation program with integrated circuit emphasis (SPICE), and its computational complexity is linear with the number of terms included. The model is also extended to CMOS gates driving distributed RLC trees and coupled multiconductor transmission lines.

Studies on dynamic characteristics of the hanger vibration using field monitoring data are important for the design and evaluation of high-speed railway truss arch bridges. This paper presents an analysis of the hanger's dynamic displacement responses based on field monitoring of Dashengguan Yangtze River Bridge, which is a high-speed railway truss arch bridge with the longest span throughout the world. The three vibration parameters, i.e., dynamic displacement amplitude, dynamic load factor and vibration amplitude, are selected to investigate the hanger's vibration characteristics in each railway load case including the probability statistical characteristics and coupled vibration characteristics. The influences of carriageway and carriage number on the hanger's vibration characteristics are further investigated. The results indicate that: (1) All the eight railway load cases can be successfully identified according to the relationship of responses from strain sensors and accelerometers in the structural health monitoring system. (2) The hanger's three vibration parameters in each load case in the longitudinal and transverse directions have obvious probabilistic characteristics. However, they fall into different distribution functions. (3) There is good correlation between the hanger's longitudinal/transverse dynamic displacement and the main girder's transverse dynamic displacement in each load case, and their relationships are shown in the hysteresis curves. (4) Influences of the carriageway and carriage number on the hanger's three parameters are different in both longitudinal and transverse directions; while the influence on any of the three parameters presents an obvious statistical trend. The present paper lays a good foundation for the further analysis of train-induced hanger vibration and control.