Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

Maximum likelihood decoding of convolutional codes by Viterbi decoding method is an effective error correcting technique. However, little study on Viterbi decoding of high rate codes has been done since the number of paths entering each trellis state increases as the code rate increases. This paper presents a new maximum likelihood decoding of convolutional codes of rate (n ‐ 1)/n using a trellis. the trellis is drawn according to the state transitions of the syndrome former of the code, and has only one or two paths entering each state rather than 2n‐1 paths as in the case of conventional trellises. Thus, we can replace the 2n‐1‐ary comparisons at each state needed in the conventional Viterbi decoding for the code of rate (n ‐ 1)/n by binary comparisons. the implementation of maximum likelihood decoders for high rate convolutional codes is simplified greatly by this approach. Moreover, this decoding method shows the same performance as that of conventional Viterbi decoding method from the viewpoint of selecting the maximum likelihood code sequence.

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

Convolutional codes are used extensively in numerous applications in order to achieve reliable data transfer. In this paper, the parameters of Convolutional codes are introduced and used to investigate its applications, characteristics and performance when employed as inner and outer code in decoding method. To evaluate the parameters, four schemes of Convolutional codes: non-systematic-recursive, systematic-recursive, non-systematic-non-recursive and systematic-non-recursive; are applied. In addition, the implementation of BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm is discussed by applying APP-SISO (a posteriori probabilities — Soft Input Soft Output) decoding for Convolutional codes. The proposed scheme employing inner and outer decoding of Convolutional codes are analysed and compared by using EXIT characteristic of Convolutional decoders. The channel capacity measurements for different rates inner Convolutional codes are described by using BPSK modulation over AWGN channel. BER performances of outer decoding of Convolutional codes are observed for different schemes which are described the process of area beneath in the inverted EXIT function. This is essential to obtain better performance of BER plot indeed. The result shows that inner decoding of Convolutional codes is the best performance for the EXIT function, particularly for non-systematic-recursive. However, outer decoding of this code has not good performance due to having quite larger area beneath than inner code.

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

A reduced complexity algebraic type algorithm is described for decoding of convolutional codes over GF(q), q>2. It is founded on the same principles as algebraic-sequentia1 decoding. It is proved that for large q, the algorithm has better complexity-reliability tradeoff than the conventional Viterbi algorithm.

We introduce the notion of innovations for Viterbi decoding of convolutional codes. First, we define a kind of innovation corresponding to the received data, i.e., the input to a Viterbi decoder. Then, the structure of a scarce-state-transition (SST) Viterbi decoder is derived in a natural manner. It is shown that the newly defined innovation is just the input to the main decoder in an SST Viterbi decoder and generates the same syndrome as the original received data does. A similar result holds for quick-look-in codes as well. In this case, however, the precise innovation is not defined. We see that this innovation-like quantity is related to the linear smoothed estimate of the information. The essence of innovations approach to a linear filtering problem is first to whiten the observed data, and then to treat the resulting simpler white-noise observations problem. In our case, this corresponds to the reduction of decoding complexity in the main decoder in an SST Viterbi decoder. We show that the distributions related to the main decoder (i.e., the input distribution and the state distribution in the code trellis for the main decoder) are much biased under moderately noisy conditions. We see that these biased distributions actually lead to the complexity reduction in the main decoder. Furthermore, it is shown that the proposed innovations approach can be extended to maximum-likelihood decoding of block codes as well.

We introduce a very efficient (linear-time) method for finding the best metrics from among a number of contenders during breadth-first decoding of block or convolutional codes. This method can provide a sorted set of survivor metrics during M algorithm decoding of binary linear block codes using only /spl Lambda/1 comparisons in the worst case. This is a significant improvement over comparison-based sorting, which requires O(M log/sub 2/ M) comparisons. A similar improvement is attained over Hadian and Sohel's comparison-based selection method (where the best metrics are found without regard to order). The method is also readily applicable to the decoding of convolutional codes. >

A new non-binary decoding method, which is called Yaletharatalhussein decoding algorithm, is designed and implemented for decoding non-binary convolutional codes which is based on the trellis diagram representing the convolutional encoder. Yaletharatalhussein decoding algorithm outperforms the Viterbi algorithm and other algorithms in its simplicity, very small computational complexity, decoding reliability for high states TCM codes that suitable for Fourth-Generation (4G), decreasing errors with increasing word length, and easy to implement with real-time applications. The proposed Yaletharatalhussein decoding algorithm deals with non-binary error control coding of the convolutional and TCM codes. Convolutional codes differ from block codes in that a block code takes a fixed message length and encodes it, whereas a convolutional code can encode a continuous stream of data, and a hard-decision decoding can easily be realized using the Yaletharatalhussein algorithm. The idea of non-binary codes has been extended for symbols defined over rings of integers, which outperform binary codes with only a small increase in decoding complexity. The simulation results show that the performance of the nonbinary TCM-based Yaletharatalhussein algorithm outperforms the binary and non-binary decoding methods.

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost is examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/s constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

Tighter upper bounds on the error event and the bit error probabilities, respectively, for maximum-likelihood decoding of binary convolutional codes on the binary symmetric channel are derived from upper bounds previously published by Viterbi [1]. The measured bit error rate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P_b</tex> for a constraint length 3 decoder has been plotted versus the channel transition probability <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</tex> and shows close agreement with the improved bound on the bit error probability.

When a scarce state transition (SST) Viterbi decoder is used to decode general nonsystematic convolutional codes (not included among quick look‐in (QLI) codes), metrics based on the maximum a posteriori probability (MAP) estimation method must be computed in order for the main decoder to operate under the criterion of minimizing the decoding error probability. In this case, however, it becomes necessary to extend the original code trellis structure by introducing augmented trellis states in order to incorporate the newly induced correlation among the apparent information sequence.This paper shows that the extended trellis degenerates into the original one as the channel error probability q approaches one‐half. By performing an equivalent transformation of metrics, it is shown also that the branch metrics derived based on the MAP estimation method converge to those computed using the conventional one as q approaches one‐half.

An efficient parallel processing mode is proposed for the implementation of fast forward-only iterative belief propagation decoding of orthogonal convolutional codes based on one-step decoding. In the proposed parallel processing mode, the iterative decoding of orthogonal convolutional codes makes use of the complete set of orthogonal parity-check equations on each information symbol, thus avoiding the error performance loss. The proposed parallel processing allows the speed of iterative decoding to approach that of one-step decoding. Therefore, an advantageous tradeoff can be available between data rate and latency.

An optimal and a sub-optimal MAP decoder for a tail-biting convolutional code are presented. Necessary conditions for the existence of a tail-biting circle for recursive systematic convolutional (RSC) codes are stated. The performance of a parallel-concatenated convolutional code (PCCC) with tail-biting RSC component codes and trellis terminated RSC component codes are compared.

Decoding using the dual trellis is considered as a potential technique to increase the throughput of soft-input soft-output decoders for high coding rate convolutional codes. However, the dual Log-MAP algorithm suffers from a high decoding complexity. More specifically, the source of complexity comes from the soft-output unit, which has to handle a high number of extrinsic values in parallel. In this paper, we present a new low-complexity sub-optimal decoding algorithm using the dual trellis, namely the dual Max-Log-MAP algorithm, suited for high coding rate convolutional codes. A complexity analysis and simulation results are provided to compare the dual Max-Log-MAP and the dual Log-MAP algorithms. Despite a minor loss of about 0.2 dB in performance, the dual Max-Log-MAP algorithm significantly reduces the decoder complexity and makes it a first-choice algorithm for high-throughput high-rate decoding of convolutional and turbo codes.

The wireless communication industry is currently experiencing a tremendous growth. For Wireless LAN applications, the IEEE 802.11 multiple standards have been widely adopted for the short-range communication in the two ISM bands of 2.45 GHz and 5.1-5.8 GHz. This results in an increasing demand for highly integrated transceivers of lower power consumption and small die sizes. The frequency synthesizer, which is usually formed by a Phase-Locked Loop (PLL), is a major and critical component of a wireless transceiver because it operates at high frequency and consumes a very large portion of the total power consumption in the transceiver. Currently, there exist several different standards of operation; thus a multi-standard frequency synthesizer is desirable for operations under different wireless systems. The performance in power consumption and channel selection of a frequency synthesizer are limited by the two most important building blocks, namely the frequency divider and voltage-controlled oscillator (VCO). The objective of this project is to design the most critical building blocks for the multi-GHz frequency synthesizers. All proposed circuits are realized on cost effective CMOS technology (0.18 m CMOS process) rather than bipolar, SiGe and GaAs technologies. The power consumption and the operating frequency of PLL circuits will be analyzed in details. The power consumption reduction and speed enhancement are realized through novel topologies proposed for the frequency dividers, which dominate the overall power consumption and speed performance of the PLL. A 1 V 4 mW 10 GHz divide-by-2 unit is proposed by using the modified dynamic MOS Current Mode Logic structure in post-layout simulation.