Order statistics on optically interconnected multiprocessor systems

This paper examines the computing power of optical parallel computer systems. We consider the proposed Array of Processors with optical Pipelined Buses (APPB) in particular, where processors communicate with each other via a spanning optical bus. APPB allow simultaneous access by multiple processors to the optical bus through message pipelining, thus overcoming the bottlenecks caused by exclusive access when employing electronic buses. We give an overview of this model of parallel computation, and then examine the computing power of APPB by demonstrating its capability to efficiently emulate the CRCW PRAM model. We show that an APPB is almost as powerful as a CRCW PRAM. That is, an APPB can emulate a CRCW PRAM with only a small degradation in time performance.

Order statistics on a hypercube

Efficient implementation of global computations on a linear array of processors is complicated due to the small communication bandwidth and the large communication diameter of the array. This paper presents efficient parallel techniques for partitioning, movement, and reduction of data on linear arrays. Also, efficient data structures are used to enable fast sequential access of query points within each processor. This combination of serial and parallel techniques is used to derive an optimal parallel algorithm for computing the convex hull of each connected region in an n×n image. The algorithm takes O(n 2/p) time on a linear array with p processors, where 1≤p≤n/log n. This result is processor-time optimal since an optimal sequential algorithm takes O(n 2) to solve the problem. Thus, a linear array with n/log n processors can solve the above problem in O(n log n) time. In comparison, a two dimensional mesh-connected array of processors can solve this problem in O(n) time using n 2 processors. The processor-time product for the mesh is O(n 3), which is not optimal.KeywordsConvex HullExtreme PointLinear ArrayLocal MemoryQuery PointThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

We demonstrate quantum well tri-state logic devices for possible use in optical bus architectures. These optical devices are analogous to the tri-state devices often used in electronic buses, where each device can be actively on, actively off, or disabled with at most one device on the bus active at a time. We show two methods of generating these tri-state data, one using tri-state quantum well modulators and one using optical tri-state self-electrooptic effect devices, and we demonstrate a simple optical bus consisting of two such devices. Finally, we comment on the limitations on the number of devices that can be connected to a bus of this type.

Efficient and scalable quicksort on a linear array with a reconfigurable pipelined bus system

We present a fast algorithm for sorting on a linear array with a reconfigurable pipelined bus system (LARPBS), one of the recently proposed parallel architectures based on optical buses. Our algorithm sorts N numbers in O(log N log logN) worst-case time using N processors. To our knowledge, the previous best sorting algorithm on this architecture has a running time of O(log2N).KeywordsLinear ArrayRecursive CallSorting AlgorithmMerging AlgorithmDestination ProcessorThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

We present two fast algorithms for sorting on a linear array with a reconfigurable pipelined bus system (LARPBS), one of the recently proposed parallel architectures based on optical buses. In our first algorithm, we sort N numbers in O(log N log log N) worst-case time using N processors. In our second algorithm, we sort N numbers in O((log log N)/sup 2/) worst-case time using N/sup 1+/spl epsi// processors, for any fixed /spl epsi/ such that 0 < /spl epsi/ < 1. Our algorithms are based on a novel deterministic sampling scheme for merging two sorted arrays of length N each in O(log log N) time on an LARPBS with N processors. To our knowledge, the previous best sorting algorithm on this architecture has a running time of O((log N)/sup 2/) using N processors.

The application of parallel computers to reservoir simulation is studied with the aid of two recently introduced Multiple Instruction, Multiple Data (MIMD) computers. The problems posed by reservoir simulators are shown to be particularly well suited for such parallel computers* Fundamental parallel programming techniques using Fortran are presented for the Hetrogeneous Element Processor (HEP) produced by Denelcor and the iPSC Hypercube produced by Intel. These techniques are then applied to two of the most time consuming tasks in reservoir simulation: forming the matrix coefficients and producing a sparse matrix solution. The problem of parallel formation of sparse matrix coefficients is addressed for the single and multiphase cases using both black oil and compositional fluid models. Parallel sparse matrix solution is addressed by considering D4 ordered Gaussian elimination, and the multigrid, conjugate gradient, and Successive Over-Relaxation (SOR) methods. Three parallel algorithms based on SOR are developed to illustrate the possible diversity of parallel algorithms. The red-black and multicolored SOR methods which are often used on vector machines are shown to be easily adaptable to parallel MIMD machine. Matrix partitioning and a new method of iteration pipelining are also presented as parallel SOR methods. The various SOR algorithms, in parallel form, are mapped onto the HEP to illustrate the speedups currently possible on an MIMD machine. Projections are made on the future importance of these types of machines to reservoir simulation.

Effective fault tolerance techniques are essential for improving the reliability of multiprocessor systems. At the same time, fault tolerance must be achieved at high speed to meet the real-time constraints of embedded systems. While parallelism has often been exploited to increase performance, to the best of our knowledge, there has been no previously reported work on parallel reconfiguration of mesh-connected processor arrays with faults. This paper presents two parallel algorithms to accelerate reconfiguration of the processor arrays. The first algorithm reconfigures a host array in parallel in a multithreading manner. The threads in the parallel algorithm execute independently within a safe rerouting distance. The second algorithm is based on a divide-and-conquer approach to first generate the leftmost segments in parallel and then merge the segments in parallel. When compared to the conventional algorithm, simulation results from a large number of instances confirm that the proposed algorithms significantly accelerate the reconfiguration without loss of harvest.

Sorting appears the most attention among all computational tasks over the past years because sorted data is at the heart of many computations. Sorting is of additional importance to parallel computing because of its close relation to the task of routing data among processes, which is an essential part of many parallel algorithms. Many parallel sorting algorithms have been investigated for a variety of parallel computer architectures. In this paper, three parallel sorting algorithms have been implemented and compared in terms of their overall execution time. The algorithms implemented are the odd-even transposition sort, parallel merge sort and parallel shell sort. Cluster of Workstations or Windows Compute Cluster has been used to compare the algorithms implemented. The C# programming language is used to develop the sorting algorithms. The MPI library has been selected to establish the communication and synchronization between processors. The time complexity for each parallel sorting algorithm will also be mentioned and analyzed.

Hashing techniques have long been used to efficiently store and locate data indexed by key. Recently, parallel hashing algorithms have been developed that allow table insertion of many keys in a few parallel steps. The analyses of these algorithms have focused on the expected number of steps required, ignoring the issue of work complexity. As a result, these algorithms have not been work efficient. In this paper, we present a parallel hashing algorithm that is shown to be work efficient because it performs no more work than its serial counterpart. An analysis of its behavior shows that it performs S = O(log n) expected parallel steps and W = O(n) expected work. Many parallel algorithms can make use of hashing as a core step. Procedures such as histogramming, set difference, keyed reduction and dictionary lookup can be formulated using a general hash routine. Thus, parallel hashing is an important fundamental parallel operation. The above applications may also be implemented using sorting as the core step. While the use of parallel hashing has been generally accepted in the folklore of parallel computing, a dearth of literature about the expected performance of such algorithms has led many to favor the use of sorting. This paper sheds light on the performance that may be achieved using parallel hashing algorithms and should lend credibility to their use. Performance data collected from an implementation of our algorithms on the Connection Machine CM-2 and CRAY Y-MP show that it is faster than sorting by up to a factor of four on both machines. These data show that the total time required by the algorithm is more closely related to the amount of work performed, rather than the parallel step count. Our results indicate that work efficiency is an important consideration when trying to achieve high performance on parallel machines.

Recent work on the problem of mapping pipelined or parallel computations onto linear array, shared memory, and host-satellite systems is extended. It is shown how these problems can be solved even more efficiently when computation module execution times are bounded from below, intermodule communication times are bounded from above, and the processors satisfy certain homogeneity constraints. The improved algorithms have significantly lower time and space complexities than the more general algorithms: in one case, an O(nm/sup 3/) time algorithm for mapping m modules onto n processors is replaced with an O(nm log m) time algorithm, and the space requirements are reduced from O(nm/sup 2/) to O(m). Run-time complexity is reduced further with parallel mapping algorithms based on these improvements, which run on the architectures for which they create mappings.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Randomized self-routing algorithms for Clos networks

This paper examines the effectiveness of load balancing strategies for ray tracing on large parallel computer systems and cluster computers. Popular static load balancing strategies are shown to be...

The authors consider parallel algorithms for online (real-time) data compression that use dynamic (adaptive) learning by textual substitution. The author's model of computation is a systolic pipe, in which processors are arranged in a linear array (each processor connected only to its left and right neighbors). He first considers an array of processors that is large enough to accommodate one dictionary entry per processor. He then discusses using an existing parallel machine where the number of available processors might be limited. >