Proposed digital-correlator design with four-valued threshold logic

The article proposes a method for synthesizing ternary binary logic functions using a multi-threshold element, which significantly extends the capabilities of ternary logic compared to traditional binary logic. The aim of the work is to develop an algorithm for synthesizing ternary logic functions, based on the use of a multi-threshold element, which simplifies the design of logical circuits and reduces energy consumption while maintaining high data processing speed. The study includes a comparative analysis of ternary and binary logic functions, allowing an assessment of the advantages of ternary logic, particularly its ability to process more values than binary logic, which opens up new possibilities for creating more efficient computing devices. Specifically, ternary logic can reduce the complexity of circuits and hardware resource usage, while also enhancing performance in tasks where energy efficiency is critical. An essential part of the research is the development of an algorithm for synthesizing ternary binary logic functions based on a four-threshold multi-valued element. Furthermore, a software module was implemented to automate the synthesis of ternary functions. The program not only generates a graphical representation of the logical circuit but also formulates the analytical expression corresponding to the given logical function. This significantly simplifies the design and analysis of logical systems and enhances the efficiency of computations. Considering the high potential of ternary logic, the results of this work are significant not only for theoretical research but also for practical applications in the development of new computing devices and technologies. The further development of these ideas could contribute to the progress in computational systems working on new principles and open up new possibilities for optimizing technological processes in various fields of science and engineering.

In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. 
 Keywords: Ternary logic, Ternary logic gates, VHDL language.

Advances in multiple-valued logic (MVL) have been inspired, in large part, by advances in integrated circuit technology. Multiple-valued logic has matured to the point where four-valued logic is now part of commercially available VLSI IC's. Besides reduction in chip area, MVL offers other benefits such as the potential for circuit test. This paper describes the historical and technical background of MVL, and areas of present and future application. It is intended, as well, to serve as a tutorial for the nonspecialist.

In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter (SI), positive inverter (PI) and negative inverter (NI) and ternary basic gates such as AND, NAND, OR and NOR gates are designed. Furthermore, the half adder circuits developed which assists to develop complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed circuits are investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

Traditional digital circuits use binary logic for implementation which requires more number of data lines to carry information. In contrast to binary, multiple-valued logic (MVL), digital circuits require less number of data lines to represent information. MVL uses more than two levels to represent a number; thereby reducing the number of interconnects. One of its kind is ternary logic, (known as radix-3 system) and uses three different voltage levels, whereas the other quaternary logic (radix-4 system) uses four different voltage levels to represent a number. Various digital circuits are implemented using MVL which potentially reduces the chip area, power consumption, and propagation delay. This article discusses about fundamental concepts of ternary, quaternary system and reviews some of arithmetic and logic circuits using ternary and quaternary logic. This paper also presents different methodologies used to implement arithmetic and logic operations using MVL. It is found that, due to the effective utilization of interconnects, MVL digital circuits provide better performance over binary digital circuits in terms of area, power, and delay.KeywordsNumber systemArithmetic and Logic circuitsChip areaMultiple-Valued Logic (MVL)Quaternary logicTernary logicTiming delayVLSI

A large number of advantages are offered by multi level inverters and hence a number of topologies are proposed over the years. There has been an evolution of new topologies with reduced number of switching devices. Not a single topology is enough for all the applications, so these topologies are developed with orientation based upon the application. Some topologies suites one application but do not suite well to the other application. The paper presents a comparative modelling analysis of a number of multilevel inverter topologies with reduced device count with the purpose of proposing the better options out of reduced device count topologies for economic optimization of grid interface inverter.

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low‐complex, high‐speed, and energy‐efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi‐threshold graphene nanoribbon field‐effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET‐based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

Tremendous amounts of data are being generated and should be processed during the massive employment of artificial intelligence and edge/cloud computing, necessitating computers with higher capabilities. However, as Moore's Law approaches its limit, enhancing computing capability through transistor miniaturization is becoming less feasible. New strategies for “more-than-Moore” are highly preferred to drive future technological advancements. Multiple-valued logic, especially ternary logic with its superior data density compared to traditional binary logic, offers a viable route to augment computing capability while reducing chip interconnections and dynamic power consumption. Despite the growing interest in ternary logic within academia and industry, its practical application remains limited due to the increased transistor count and connections required by earlier logic gate implementations. In this thesis, we present efficient implementation methods of basic ternary logic gates based on emerging nano-electronics including two-dimensional material-based transistors. The fabricated ternary devices show high performance in DC gain and low power consumption. Additionally, compact models of the devices have been established and calibrated, facilitating the circuit design and simulation in Electronic Design Automation (EDA) tools. At the circuit level, this thesis introduces novel ternary arithmetic circuits, including adders and multipliers, that are optimized for low power consumption and minimal delay. Finally, we showcase the practical benefits of ternary logic systems in data processing through the implementation of carry-free arithmetic circuits, underscoring their potential as a transformative computing paradigm.

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beam Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.

High step-up dc-dc converters are predominantly used for interfacing low-voltage renewable sources including solar photovoltaic (SPV), fuel-cells, and DC microgrid. Several high gain topologies reported in the literature to integrate such sources, however, suffer from issues such as limited voltage boosting factor, higher device voltage stress, inability to deal with wide input voltage variations, increased device count, discontinuous input current, and so on. To address the aforementioned limitations, this article proposes a modified high gain converter. This is achieved by methodically adjusting the Z-source (ZS) converter to obtain high gain while lowering voltage stress and device count. As a result, switches with lower on-state resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(R_{ds(on)})$</tex> are employed, which facilitates reduced switching losses and enhanced efficiency. Furthermore, while drawing continuous input current, the converter has improved efficiency at lower duty ratios, which is a crucial aspect of an SPV interface converter. The implemented topology performed well when compared to similar recent topologies. Eventually, experimental waveforms validate the theoretical claims and analysis. A 93.5% peak converter efficiency has been obtained.

A delta-sigma modulator (DSM) is proposed for the direct connection to micro-electro-mechanical systems (MEMS) microphone. To reduce power, both the DAC reference voltage (VREF) and the DSM supply voltage (VDD) are reduced to 700 mV by limiting the maximum linear acoustic input range to 110 dB SPL (sound pressure level). For the low VDD operation, the switched capacitor (SC) integrators of DSM employ CMOS inverters as amplifiers. A unity-gain buffer compensates the pole error of the SC integrator; it reduces chip area by replacing the auto-zero capacitor of conventional inverter-based SC integrator. Compared to the conventional integrator, the integrator of this brief reduces the pole error from 0.3% to 0.06%, reduces the chip area and the power by 32.4% and 24.8%, respectively. The 3rd order DSM in a 65 nm CMOS process was measured to have Walden-figure of merit (FoMw) 89.3fJ/step, dynamic range (DR) 90.1 dB, signal-to-noise ratio (SNR) 87.2 dB, signal-to-noise and distortion ratio (SNDR) 86.4 dB, and power 122 uW at 10 MHz clock frequency (Fs).

Ternary Logic is the best and suitable alternative for binary logic. Binary Logic consists of 2 logic states 0 and 1 whereas ternary logic contains three states logic 0, 1 and 2. The advantages of Ternary over binary logic is it improves switching speed. This technique helps to reduce the computation steps, complexity and chip area. This paper is a study of CNTFET based ternary logic gate and improved impact on power and delay. A ternary NAND, NOR Gates are designed using Carbon nanotube transistors. The TNAND and TNOR gate circuits are simulated using the HSPICE tool. The performance parameters of the TLG using Carbon Nanotube FETs in terms of Delay are 621ps, 20.66ps, in terms of power are 0.47μW, 0.53μW

In this chapter, a new type of combinational logic circuit realization is presented. These logic circuits are based on non-DC representation of logic values . In this scheme, logic values can be represented by signals that are uncorrelated, for example, distinct values represented by independent stochastic processes (noise from independent sources). This provides a natural way of implementing multivalued logic . Signals driven over long distances could take advantage of this fact and can share interconnect lines. Alternately, sinusoidal signals can be used to represent logic values. Sinusoid signals of different frequencies are uncorrelated. This property of sinusoids can be used to identify a signal without ambiguity. This chapter presents a logic family that uses sinusoidal signals to represent logic 0 and logic 1 values. We present sinusoidal gates which exploit the anti-correlation of sinusoidal signals, as opposed to uncorrelated noise signals. This is achieved by employing a pair of sinusoid signals of the same frequency, but with a phase difference of 180°. Recent research in circuit design has made it possible to harvest sinusoidal signals of the same frequency and 180° phase difference from a single resonant clock ring , in a distributed manner. Another advantage of such a logic family is its immunity from external additive noise. The experiments in this chapter indicate that this paradigm, when used to implement binary valued logic, yields an improvement in switching (dynamic) power.

Organic multi-valued logic (MVL) circuits can substantially improve the data processing efficiency in highly advanced wearable electronics. Organic ternary logic circuits can be implemented by utilizing the negative transconductance (NTC) of heterojunction transistors (H-TRs). To achieve high-performance organic ternary logic circuits, the range of NTC in H-TRs must be optimized in advance to ensure the well-defined intermediate logic state in ternary logic inverters (T-inverters). Herein, a simple and efficient strategy, which enables the systematic control of the range and position of NTC in H-TRs is presented. Each thickness of p-/n-type semiconductor in H-TRs is adjusted to control the channel conductivity. Furthermore, asymmetric source/drain (S/D) electrode structure is newly developed for H-TRs, which can adjust the amount of hole and electron injection, independently. Based on the semiconductor thickness variation and asymmetric S/D electrodes, the T-inverter exhibits full-swing operation with three distinguishable logic states, resulting in unprecedentedly high static noise margin (≈48% of the ideal value). Moreover, a flexible T-inverter with an ultrathin polymer dielectric is demonstrated, whose operating voltage is less than 8V. The proposed strategy is fully compatible with the conventional integrated circuit design, which is highly desirable for broad applicability and scalability for various types of T-inverter production.