The Prospects for Multivalued Logic: A Technology and Applications View

Traditional digital circuits use binary logic for implementation which requires more number of data lines to carry information. In contrast to binary, multiple-valued logic (MVL), digital circuits require less number of data lines to represent information. MVL uses more than two levels to represent a number; thereby reducing the number of interconnects. One of its kind is ternary logic, (known as radix-3 system) and uses three different voltage levels, whereas the other quaternary logic (radix-4 system) uses four different voltage levels to represent a number. Various digital circuits are implemented using MVL which potentially reduces the chip area, power consumption, and propagation delay. This article discusses about fundamental concepts of ternary, quaternary system and reviews some of arithmetic and logic circuits using ternary and quaternary logic. This paper also presents different methodologies used to implement arithmetic and logic operations using MVL. It is found that, due to the effective utilization of interconnects, MVL digital circuits provide better performance over binary digital circuits in terms of area, power, and delay.KeywordsNumber systemArithmetic and Logic circuitsChip areaMultiple-Valued Logic (MVL)Quaternary logicTernary logicTiming delayVLSI

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

This paper presents addition and multiplication in Galois field using multi-valued logic. Multi-valued logic (MVL) has matured to the point where four-valued logic is now part of commercially available VLSI IC’s. Modulo-4 addition and multiplication is also presented in this paper. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice

Many-valued logics in general and 3-valued logic in particular is an old subject which had its beginning in the work of Łukasiewicz [Łuk]. Recently there is a revived interest in this topic, both for its own sake (see, for example, [Ho]), and also because of its potential applications in several areas of computer science, such as proving correctness of programs [Jo], knowledge bases [CP] and artificial intelligence [Tu]. There are, however, a huge number of 3-valued systems which logicians have studied throughout the years. The motivation behind them and their properties are not always clear, and their proof theory is frequently not well developed. This state of affairs makes both the use of 3-valued logics and doing fruitful research on them rather difficult.Our first goal in this work is, accordingly, to identify and characterize a class of 3-valued logics which might be called natural. For this we use the general framework for characterizing and investigating logics which we have developed in [Av1]. Not many 3-valued logics appear as natural within this framework, but it turns out that those that do include some of the best known ones. These include the 3-valued logics of Łukasiewicz, Kleene and Sobociński, the logic LPF used in the VDM project, the logic RM3 from the relevance family and the paraconsistent 3-valued logic of [dCA]. Our presentation provides justifications for the introduction of certain connectives in these logics which are often regarded as ad hoc. It also shows that they are all closely related to each other. It is shown, for example, that Łukasiewicz 3-valued logic and RM3 (the strongest logic in the family of relevance logics) are in a strong sense dual to each other, and that both are derivable by the same general construction from, respectively, Kleene 3-valued logic and the 3-valued paraconsistent logic.

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.

As in binary, a multiple-valued programmable logic array (PLA) realises a sum-ofproducts expression specified by the user. However, in multiple-valued logic, there are many more operations than in binary, and an important question is the choice of operations which provides the greatest number of functions for a given chip area. In this paper, we analyse various PLA configurations using operations realised in the peristaltic multiple-valued CCD technology. We compare a multiple-valued CCD PLA implementation with four other proposed designs and show that there is a significant difference in chip area required to realise the same set of functions. The basis of comparison is the set of 4-valued unary functions.

A monolithic digital-correlator circuit design is proposed and described which uses four-valued or quad threshold logic to develop its binary coded output. The use of four-valued logic provides a reduced device count, fewer signal lines and a reduced chip area. This design is compared to a conventional all-binary design of the same digital correlation function

The ultimate usefulness of a number system depends on its implementation. Multiple-valued logic has been implemented in charge-coupled devices (CCD). In this technology, logic values are encoded as charge. For example, prototype four-valued logic devices have been implemented at the University of Twente (Enschede, Holland). Hitachi has implemented a 16-valued memory that stores the equivalent of 10/sup 6/ bits. CCD is more compact than any other VLSI technology. Although it is slower than CMOS (complementary metal oxide semiconductor), it is much faster than the disk and has the potential of replacing the disk. The use of multiple-valued logic in CCD increases its storage capacity significantly. Multiple-valued logic has also been implemented in current-mode CMOS.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Tremendous amounts of data are being generated and should be processed during the massive employment of artificial intelligence and edge/cloud computing, necessitating computers with higher capabilities. However, as Moore's Law approaches its limit, enhancing computing capability through transistor miniaturization is becoming less feasible. New strategies for “more-than-Moore” are highly preferred to drive future technological advancements. Multiple-valued logic, especially ternary logic with its superior data density compared to traditional binary logic, offers a viable route to augment computing capability while reducing chip interconnections and dynamic power consumption. Despite the growing interest in ternary logic within academia and industry, its practical application remains limited due to the increased transistor count and connections required by earlier logic gate implementations. In this thesis, we present efficient implementation methods of basic ternary logic gates based on emerging nano-electronics including two-dimensional material-based transistors. The fabricated ternary devices show high performance in DC gain and low power consumption. Additionally, compact models of the devices have been established and calibrated, facilitating the circuit design and simulation in Electronic Design Automation (EDA) tools. At the circuit level, this thesis introduces novel ternary arithmetic circuits, including adders and multipliers, that are optimized for low power consumption and minimal delay. Finally, we showcase the practical benefits of ternary logic systems in data processing through the implementation of carry-free arithmetic circuits, underscoring their potential as a transformative computing paradigm.

In terms of memory, multivalued logic can be the fitting logic for the existing binary logic. Ternary logic contains three symbols in place of two symbols used in the binary logic, i.e., 0, 1, 2. More information can be stored with the help of these three symbols. SRAM cell is widely used in the digital circuit. The SRAM cell designed using the ternary logic can be used in the design of large memory arrays designed using ternary logic. The traditional ternary inverter which is used in the design of the traditional ternary SRAM cell is unable to store the proper values for the second state, there is a voltage level drop, which in turn affects the data read/write value of the SRAM cell designed using this traditional ternary inverter. Hence there is a need to design the ternary inverter cell which can give the proper output voltage level of all three states of the ternary logic. The level shift ternary inverter is designed to fulfill this disadvantage. The ternary inverter is designed in order to achieve the ideal DC characteristics, and the same level shift ternary inverter is used in the design of level shift ternary SRAM. This ternary SRAM stores the data properly at read/write signal. The traditional ternary inverter and traditional ternary SRAM, level shift ternary inverter and level shift ternary SRAM are implemented in Cadence 45 nm technology. The traditional ternary inverter consumes 2.37 μW power, and the level shift ternary SRAM consumes 2.43 μW power. The traditional ternary SRAM consumes 3.012 μW and level shift ternary SRAM consumes 3.14 μW. At the cost of a little bit increased power and the number of transistors, the traditional ternary SRAM can be replaced with level shift ternary SRAM. This level shift ternary SRAM stores all the voltage levels at all three levels. The same level shift ternary SRAM cell can be used for the design of large memory arrays.

In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter (SI), positive inverter (PI) and negative inverter (NI) and ternary basic gates such as AND, NAND, OR and NOR gates are designed. Furthermore, the half adder circuits developed which assists to develop complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed circuits are investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

Background: Multiple-Valued Logic (MVL) is the non-binary-valued system, in which more than two levels of information content are available, i.e., L>2. In modern technologies, the dual level binary logic circuits have normally been used. However, these suffer from several significant issues such as the interconnection considerations including the parasitics, area and power dissipation. The MVL circuits have been proved to be consisting of reduced circuitry and increased efficiency in terms of higher utilization of the circuit resources through multiple levels of voltage. Innumerable algorithms have been developed for designing such MVL circuits. Extended form is one of the algebraic techniques used in designing these MVL circuits. Voltage mode design has also been employed for constructing various types of MVL circuits. Novelty: This paper proposes a novel MVLTRANS inverter, designed using conventional CMOS and pass transistor logic based MVLPTL inverter. Binary to MVL Converter/Encoder and MVL to binary Decoder/Converter are also presented in the paper. In addition to the proposed decoder circuit, a 4-bit novel MVL Binary decoder circuit is also proposed. Tools Used: All these circuits are designed, implemented and verified using Cadence® Virtuoso tools using 180 nm technology library.

In this paper we present a many-valued logic programming, based on reinterpreted Belnap's 4-valued bilattice: we introduce the new semantics for a 4-valued implication by relative pseudo-complement, used for intuitionistic logics. This kind of logic programming is particularly useful for data integration with possibly incomplete and inconsistent information. We define an ontological encapsulation of the epistemic many-valued logic programs with negation, based on this bilattice, into 2-valued meta logic programs. Obtained 2-valued logic semantically reflects original epistemic many-valued logic, and can be used in order to define many-valued logic entailment and inference closure for many-valued truth assignments.

The geometry dependant threshold voltage of carbon nanotube FETs (CNFETs), has been often used to design a ternary logic family. However , for the last couple of decades , multiple-valued logic (MVL) such as ternary (base=3) or quaternary (base=4) logic styles has attracted considerable attention. MVL circuits can reduce the number of operations necessary to implement a particular mathematical function and further, have an advantage in terms of reduced area. As we progress into an era of nanotechnology , molecular devices are becoming promising alternatives to the existing silicon technology. Carbon nanotube field effect transistors (CNFETs) are being extensively studied as possible successors to silicon MOSFETs. Research has started in the earnest to understand the device physics of CNFETs as well as to explore possible circuit applications. Implementable CNTFET circuits have operational characteristics to approach the advantage of using MVL in voltage mode. In this paper through using of CNTFET characteristics, we presented new CNTFET circuit design to implement optimum quaternary Galois field logic.

Multi-valued logic (MVL) is that logic which has two or more logic values. In complex digital circuits, MVL (mainly Ternary logic) offers several advantages over binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is ideal to implement ternary logic circuits because of the threshold voltage of CNTFETs depends on the physical dimensions (chirality) of their channel. This work presents the implementation of a three-bit Ternary Prefix Adder using CNTFET technology. In this paper, a carry propagate-generate concept is used in order to implement the ternary prefix adder. A Kogge-Stone based prefix network is preferred for carry computation due to its high performance. A low power enoder is used for reducing the overall power of the adder. HSpice tool is chosen for designing this system. Simulation results show that there is a significant reduction in Power Delay Product (PDP) by 28 % compared to all other previous works.