Reconfigurable Galois Field multiplier

Introduction. The problem of mathematical safe arises in the theory of computer games and cryptographic applications. The article considers numerous variations of the mathematical safe problem and examples of its solution using systems of linear Diophantine equations in finite rings and fields. The purpose of the article. To present methods for solving the problem of a mathematical safe for its various variations, which are related both to the domain over which the problem is considered and to the structure of systems of linear equations over these domains. To consider the problem of a mathematical safe (in matrix and graph forms) in different variations over different finite domains and to demonstrate the work of methods for solving this problem and their efficiency (systems over finite simple fields, finite fields, ghost rings and finite associative-commutative rings). Results. Examples of solving the problem of a mathematical safe, the conditions for the existence of solutions in different areas, over which this problem is considered. The choice of the appropriate area over which the problem of the mathematical safe is considered, and the appropriate algorithm for solving it depends on the number of positions of the latches of the safe. All these algorithms are accompanied by estimates of their time complexity, which were considered in the first part of this paper. Conclusions. The considered methods and algorithms for solving linear equations and systems of linear equations in finite rings and fields allow to solve the problem of a mathematical safe in a large number of variations of its formulation (over finite prime field, finite field, primary associative-commutative ring and finite associative-commutative ring with unit). Keywords: mathematical safe, finite rings, finite fields, method, algorithm.

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Y}_{{2}}\text{O}_{{3}}$ </tex-math></inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Finite (Galois) field arithmetic finds applications in cryptography, error correction codes, signal processing, etc. Multiplication usually lies at the core of all Galois field computations and is a high-complexity operation. This paper addresses the problem of formal verification of hardware implementations of modulo-multipliers over Galois fields of the type F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> k, using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> k[x <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ,x <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ,⋯,x <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ] and the verification test is formulated as a Nullstellensatz proof over the finite field. A Grobner basis engine is used as the underlying computational framework. The efficiency of Grobner basis computations depends heavily upon the variable (and term) ordering used to represent and manipulate the polynomials. We present a variable (and term) ordering heuristic that significantly improves the efficiency of Grobner basis engines. Using our approach, we can verify the correctness of up to 96-bit multipliers, whereas contemporary BDDs/SAT/SMT-solver based methods are infeasible.

From the 19th century, the theory of permutation polynomial over finite fields, that are arose in the work of Hermite and Dickson, has drawn general attention. Permutation polynomials over finite fields are an active area of research due to their rising applications in mathematics and engineering. The last three decades has seen rapid progress on the research on permutation polynomials due to their diverse applications in cryptography, coding theory, finite geometry, combinatorics and many more areas of mathematics and engineering. For this reason, the study of permutation polynomials is important nowadays. In this chapter, we propose some new problems in connection to permutation polynomials over finite fields by the help of prime numbers.

This paper investigates the feasibility of a unified processor architecture to enable error coding flexibility and secure communication in low power Internet of Things (IoT) wireless networks. Error coding flexibility for wireless communication allows IoT applications to exploit the large tradeoff space in data rate, link distance and energy-efficiency. As a solution, we present a light-weight Galois Field (GF) processor to enable energy-efficient block coding and symmetric/asymmetric cryptography kernel processing for a wide range of GF sizes (2m, m = 2, 3, ..., 233) and arbitrary irreducible polynomials. Program directed connections among primitive GF arithmetic units enable dynamically configured parallelism to efficiently perform either four-way SIMD 5- to 8-bit GF operations, including multiplicative inverse, or a wide bit-width (e.g., 32-bit) GF product in a single cycle. To illustrate our ideas, we synthesized our GF processor in a 28nm technology. Compared to a baseline software implementation optimized for a general purpose ARM M0+ processor, our processor exhibits a 5-20 x speedup for a range of error correction codes and symmetric/asymmetric cryptography applications. Additionally, our proposed GF processor consumes 431μW at 0.9V and 100MHz, and achieves 35.5pJ/b energy efficiency while executing AES operations at 12.2Mbps. We achieve this within an area of 0.01mm2.

We give a new algorithm for constructing Picard curves over a finite field with a given endomorphism ring. This has important applications in cryptography since curves of genus 3 allow for smaller key sizes than elliptic curves. For a sextic CM-field $K$ containing the cube roots of unity, we define and compute certain class polynomials modulo small primes and then use the Chinese Remainder Theorem to construct the class polynomials over the rationals. We also give some examples.

After using side-channel information leaked by the FPGA chip which is embedded with a block cipher algorithm, there is a scheme called improved combinational side-channel attack. This scheme mainly aimed at logical circuits implemented in S-box in background of power consumption attack and we make a level of models by power consumption in combinational logic circuits which is engendered by glitches different from traditional sequential logical circuits which is engendered by flip in the output of register with the Hamming model. In addition, we take advantage of match algorithm in a linear model and in multivariate Gaussian model from template attack to process an important data twice and the key would be recovered. At last, we make a comparison between Hamming model and our model. And prove that this paper improved the attacking efficiency and accuracy and also provided a clue to the security cipher chip from countermeasures.

This paper proposes a method for detecting delay faults of gates in a combinational logic circuit. Assuming that a gate of the circuit has a small delay (a unit delay), the generation of a test for the circuit is described. This paper also describes the generation of the timed seven-valued calculus used in the method. The method has been applied successfully to benchmark circuits having unit delay and a fanout weighted delay. The experimental results show that the method has high fault coverage in all the circuits, and that this can be applied to the detection of gross delay faults. The proposed test method is called the ‘SD test’. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(6): 68–76, 1997

A sizing and constrained optimization algorithm for CMOS (complementary metal-oxide semiconductor) combinational logic circuits is presented. A constrained optimization problem is first transformed to a Lagrange multiplier form with a suitable cost function. Various techniques are applied to choose optimization variables, initial guess, and optimization direction and to reduce the occurrence of local minimum. As an example, the algorithm is applied to the minimization of power dissipation with a fixed delay constraint for the sizing of CMOS (complementary metal-oxide semiconductor) combinational logic circuits. It is shown that due to the proper choice of optimization variables, initial guess values, and optimization directions and the reduced occurrence of local minimum in the algorithm, the efficiency of the sizing and optimization are improved. The algorithm can be applied to many other circuit optimization problems with constraints.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size.

According to the goal of independent college to cultivate application service-oriented talents.The paper presents the field programmable gate array(FPGA),Quartus II and Verilog HDL knowledge to the teaching method in the teaching of digital logic circuit using the combinational logic circuits and sequential logic circuits as a design example.The teaching practice shows that this teaching method can motivate students interest in learning.It plays a positive role in promoting students practice ability and innovation consciousness,thus enhance the teaching quality.

The problem of exponentiation over a finite field is to compute A e for a field element A and a positive integer e. This problem has many useful applications in cryptography and information security. In this paper, we present an efficient exponentiation algorithm in optimal extension field (OEF) GF(p m ), which uses the fact that the Frobenius map, i.e., the p-th powering operation is very efficient in OEFs. Our analysis shows that the new algorithm is twice as fast as the conventional square-and-multiply exponentiation. One of the important applications of our new algorithm is random generation of a base point for elliptic curve cryptography, which is an attractive public-key mechanism for resource-constrained devices. We present a further optimized exponentiation algorithm for this application. Our experimental results show that the new technique accelerates the generation process by factors of 1.62–6.55 over various practical elliptic curves.

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.

The scalability problem is hard to overcome in the evolutionary design of the logic circuits. In this paper, a hybrid algorithm of Generalized Disjunction Decomposition and Evolutionary Repair is proposed, which is also embedded with a novel technique for compressing outputs. This hybrid algorithm aims at evolving the relatively large combinational logic circuits automatically. The experimental results demonstrate that the hybrid algorithm could evolve the relatively large circuits successfully.

Single-protein-based devices that integrate signal sensing with logical operations to generate functional outputs offer exceptional promise for monitoring and modulating biological systems. Engineering such intelligent nanoscale computing agents is challenging, as it requires the integration of sensor domains into a functional protein via intricate allosteric networks. We incorporate a rapamycin-sensitive sensor (uniRapR) and a blue light-responsive LOV2 domain into human Src kinase, creating a protein device that functions as a noncommutative combinatorial logic circuit. In our design, rapamycin activates Src kinase, causing protein localization to focal adhesions, whereas blue light exerts the reverse effect that inactivates Src translocation. Focal adhesion maturation induced by Src activation reduces cell migration dynamics and shifts cell orientation to align along collagen nanolane fibers. Using this protein device, we reversibly control cell orientation by applying the appropriate input signals, a framework that may be useful in tissue engineering and regenerative medicine.