Reducing threading dislocation density in GaSb photovoltaic devices on GaAs by using AlSb dislocation filtering layers

ABSTRACTWe have studied the possibilities of reducing the threading dislocation (TD) density in GaAs on Si using free side wall growth on patterned Si substrates and/or using a soft ZnSe interlayer in combination with post growth annealing procedures. TD densities were accurately determined using large area plan view TEM and were found to be unaffected by proximity to free side walls and by the ZnSe interlayer. Post growth heat treatments led to a factor of ∼2 reduction in TD density and to bunching of dislocations throughout the thickness of the film.

Evolution of threading dislocations in MOCVD-grown GaN films on (1 1 1) Si substrates

In order to study the luminescent efficiency of InGaAs quantum wells on Si via SiGe interlayers, identical In0.2Ga0.8As quantum well structures with GaAs and Al0.25Ga0.75As cladding layers were grown on several substrates by an atmospheric metalorganic vapor deposition system. The substrates used include GaAs, Si, Ge, and SiGe virtual substrates. The SiGe virtual substrates were graded from Si substrates to 100% Ge content. Because of the small lattice mismatch between GaAs and Ge (0.07%), high-quality GaAs-based thin films with threading dislocation densities <3×106 cm−2 were realized on these SiGe substrates. Quantitative cathodoluminescence was used to compare the luminescent efficiency of the quantum well structure on the different substrates and cross-sectional transmission electron microscopy was used to characterize dislocation densities. Our results show that the InGaAs quantum wells grown on the GaAs substrates have the highest luminescent efficiencies due to the lowest dislocation densities. Interestingly, InGaAs quantum wells grown on the SiGe virtual substrates outperform those on Ge substrates, both in terms of luminescent efficiency and dislocation density. This difference is attributed to the variation in thermal expansion coefficient (α) and its impact on defect structure during the process cycle. The SiGe virtual substrate has a smaller α compared to a Ge substrate because of the smaller α of the Si substrate, which helps minimize compressive strain in the quantum well layer during the temperature decrease from the growth temperature. Consequently, fewer misfit dislocations are created between the quantum well and cladding interfaces. These misfits can greatly affect the luminescent efficiency since they can act as recombination sites. In general, the efficiencies of the quantum wells on the SiGe and Ge substrates were affected only by higher misfit dislocation densities, whereas the quantum wells on the Si substrate had low efficiency due to high threading dislocation density.

Heterojunction bipolar transistors (HBTs) with GaAs0.825P0.175 bases and collectors and In0.40Ga0.60P emitters were integrated monolithically onto Si substrates. The HBT structures were grown epitaxially on Si via metalorganic chemical vapor deposition, using SiGe compositionally graded buffers to accommodate the lattice mismatch while maintaining threading dislocation density at an acceptable level (∼3 × 106 cm−2). GaAs0.825P0.175 is used as an active material instead of GaAs because of its higher bandgap (increased breakdown voltage) and closer lattice constant to Si. Misfit dislocation density in the active device layers, measured by electron-beam-induced current, was reduced by making iterative changes to the epitaxial structure. This optimized process culminated in a GaAs0.825P0.175/In0.40Ga0.60P HBT grown on Si with a DC current gain of 156. By considering the various GaAsP/InGaP HBTs grown on Si substrates alongside several control devices grown on GaAs substrates, a wide range of threading dislocation densities and misfit dislocation densities in the active layers could be correlated with HBT current gain. The effect of threading dislocations on current gain was moderated by the reduction in minority carrier lifetime in the base region, in agreement with existing models for GaAs light-emitting diodes and photovoltaic cells. Current gain was shown to be extremely sensitive to misfit dislocations in the active layers of the HBT—much more sensitive than to threading dislocations. We develop a model for this relationship where increased base current is mediated by Fermi level pinning near misfit dislocations.

The reduction of threading dislocation density due to their mutual interactions in GaSb thin films grown on (001) GaAs substrates by molecular beam epitaxy has been investigated. The effectiveness of several buffer layer schemes including GaSb/AlSb strained layer superlattice and buffers for threading dislocation suppression was evaluated. High‐resolution transmission electron microscopy shows that the GaSb/GaAs interface consists of a highly periodic network of 90° pure edge misfit dislocations, with an average spacing close to that for a fully relaxed system. This results in relatively low threading densities in the GaSb epilayer, despite their large lattice constant mismatch (8.2%). The threading dislocation density as a function of GaSb film thickness was determined by plan‐view transmission electron microscopy and was found to decrease with film thickness due to mutual interactions among dislocations. It was found that a strained layer superlattice of GaSb/AlSb, with each layer close to its critical thickness, is the most effective in threading density reduction.

The high density of threading dislocations, often leading to the formation of invertedhexagonal pits in InGaN/GaN heterostructures on sapphire substrates, lowersthe radiative efficiency of light emitting devices. In this study, a cracked AlGaNtemplate has been implemented as a strain-relaxed layer for subsequent growth ofInGaN/GaN heterostructures. The detailed electron microscopy and surface topographicanalyses show that such a template has led to a reduction of threading dislocationdensity especially for screw dislocations and V-pits in the overgrown InGaN/GaNlayers. The relaxed regrowth of such heterostructures also leads to an improvedcrystalline quality and a higher In incorporation in InGaN. The improvement inthe optical and structural quality of these InGaN/GaN layers is investigated bymeans of photoluminescence spectroscopy and transmission electron microscopy.

To fabricate deep-ultraviolet (DUV) LEDs with high efficiency, the crystallinity of AlGaN must be improved, which is strongly influenced by the quality of the underlying AlN template. Face-to-face annealed sputter-deposited AlN templates (FFA Sp-AlN) on sapphire substrates have achieved screw and edge threading dislocation densities (TDDs) as low as 10⁴cm⁻² and 10⁷cm⁻², respectively. The reduction of TDDs in FFA Sp-AlN and the resulting surface flattening of AlₓGa₁₋ₓN layers grown on it play critical roles in enhancing the external quantum efficiency (EQE). Following MOVPE homoepitaxial AlN growth, the FFA Sp-AlN exhibits an atomically smooth surface morphology. The EQE of UV-C LEDs fabricated on FFA Sp-AlN increased as the TDDs decreased. A maximum EQE of 8.0% and output power of 6.6mW at a 20mA injection current were achieved, with a peak emission wavelength of 263nm. Furthermore, we successfully fabricated LEDs with emission wavelengths of 230nm and 236nm on FFA Sp-AlN templates.

The detrimental effects of structural defects, micro-twins (MTs) and threading dislocations (TDs), on electron mobility have been investigated for InSb quantum wells (QWs) at room temperature (RT). The constants that are necessary to calculate the electron-mobility limits of these defects were determined by a least-squares-based method that has an advantage of clear representation of the analytical results in a two-dimensional space. Based on a mathematical consideration, a general method of converting electron-mobility limits into percentage impacts upon the total electron mobility was developed. Percentage-mobility-impact analyses showed that, when InSb QWs grown on on-axis (001) GaAs substrates have a TD density of 8.7 × 108 – 3.2 × 109/cm2, 21–14 and 18–45% of electron-mobility degradation are attributed to MTs and TDs, respectively, at RT. The use of 2° off-axis (001) GaAs substrates reduces MT densities in InSb QWs, resulting in a suppression of the MT mobility impact to 3–2% and a complementary slight increase of the TD mobility impact to 22–51% in the same TD density range. This considerable TD mobility limit indicates that it should be possible to improve RT electron mobility in InSb QWs grown on 2° off-axis (001) GaAs substrates, by means of reducing TD density further (< 8.7 × 108/cm2). Although the mobility impacts due to phonons in InSb QW grown on-axis and 2° off-axis (001) GaAs substrates are 54–36 and 67–42%, respectively, phonon scattering is not a single dominant scattering factor: MTs and TDs have also substantial negative impacts upon RT electron mobilities in InSb QWs.

Relaxed Si1−xGex layers on Si(001) serve as virtual substrates for strained Si or Ge layers. However, plastically relaxed layers inevitably contain misfit and threading dislocations, negatively affecting devices. Deposition of a SiGe layer on the backside of the substrate introduces a dislocation reservoir at the wafer edge that can reduce the threading dislocation density (TDD) of Si0.98Ge0.02/Si layers, as these preexisting dislocations start gliding toward the wafer center upon reaching the critical thickness. Here, we show that this low-strain system can be used effectively to study dislocation glide kinetics. In agreement with the literature, dislocation glide is a thermally activated process with an activation energy of 2.12–2.16 eV. Near the critical thickness, relaxation is sluggish and inefficient due to the linear dependence of the glide velocity on excess stress. At lower growth rates, dislocations from the edge reservoir are activated in a lower density due to the increase in the critical thickness through partial strain relaxation by already activated dislocations. Contrary to common models, here, the lowest possible growth rate is not essential for minimizing the TDD. Instead, a careful balance between low and high growth rates is beneficial. Overcoming the initial sluggish and inefficient relaxation phase is critical while also avoiding accumulation of strain energy, and, therefore, the activation of dislocation sources. Only in a later stage of buffer growth, the growth rate should be reduced to a minimum. With this method, the TDD of strain relaxed Si0.84Ge0.16 layers is reduced to 7 × 104 cm−2.

The influence of annealing conditions on the crystallinity of Ge deposited on Si(001) is investigated. Ge deposited with postannealing at 800 °C and 850 °C, five cycles of postannealing at 750 °C and 850 °C (temperature-swing postannealing) and several cycles of annealing at 800 °C or 850 °C during the Ge growth by interrupting the deposition step (cyclic annealing) are compared. To check the threading dislocation density (TDD) of the deeper part of the Ge, thinning by HCl vapor phase etching (VPE) followed by Secco defect etching is performed for 5 μm thick Ge of all three annealing variants. By comparing the TDD of the same Ge thickness with and without HCl VPE, TDD reduction by VPE is observed for the sample using the cyclic annealing process only. Lower TDD is observed at higher postannealing temperature. By the five cycles of temperature swinging, TDD becomes around a half compared to conventional postannealing at 850 °C. In the case of the cyclic annealing process significant improvement of TDD is observed with increasing Ge thickness. Even at a maximum temperature of 800 °C, the same or lower TDD levels were observed for higher than 2 μm thick Ge compared to that with five cycles of temperature-swing postannealing. For the sample with cyclic annealing at 800 °C, a lower Si diffusion length into Ge is also observed for the cyclic annealing process indicating a lower thermal budget. A lower amount of tilted Ge planes at the interface is confirmed showing higher crystal quality also in the deeper part of the Ge layer.

Formation of interfacial misfit dislocation in GaSb/GaAs heteroepitaxy via anion exchange process

Epitaxial lateral overgrowth (ELO) has been used to reduce threading dislocation (TD) densities in GaN. This paper reports transmission and scanning electron microscopy studies of TDs in GaN films grown by ELO on GaN nanocolumns produced either during growth by MBE (method 1), or by self‐organised patterning on a uniform layer grown by MOCVD (method 2). In method 1, isolated nanocolumns grew without TDs, but some TDs formed when nanocolumns coalesced. Although some of these TDs extended through the overlayer, extensive lateral migration of others, depending on the dislocation type, led to dislocation annihilation, lowering the overall TD density. In method 2, a similar process of lateral migration of TDs was observed during ELO, resulting in a continuous GaN overlayer with TD densities less than 108 cm–2. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

We report on the growth of near-minimum bandgap (0.1 eV) bulk InAs0.54Sb0.46 on GaAs with pronounced photoluminescence. Combining strain-mediating techniques effectively manages the ∼10% lattice mismatch. An interfacial misfit (IMF) dislocation array allows a GaAs substrate and a GaSb buffer layer to act as a direct substitute for a conventional GaSb substrate. We further increase the lattice constant with a linearly graded metamorphic buffer layer of AlGaInSb, upon which we grow an AlInSb virtual substrate with the targeted lattice constant of the active InAsSb region. We observe that the graded buffer not only manages the mismatch between GaSb and InAsSb but also reduces the density of residual threading dislocations from the GaSb/GaAs IMF by a factor of ∼10×. Material characterization demonstrates the viability of using the coupled approach of metamorphic, graded buffers and IMF arrays to manage the large lattice mismatch between the substrate and the mixed group V ternary InAsSb.

We have investigated the structural characteristics of II-VI separate confinement heterostructure lasers grown on GaAs substrates and containing Zn1−xMgxSySe1−y quaternary cladding layers, ZnSe or ZnSySe1−y guiding layers and Zn1−zCdzSe quantum well active layers. The study was performed with a combination of transmission electron microscopy and high resolution x-ray diffraction techniques. We found that the quaternary cladding layers remain pseudomorphic to the GaAs substrate although they can be lattice mismatched up to 0.1%. When the 0.5-μm-thick optical guiding layer contains ZnSe, there is partial relaxation of the laser structure by misfit dislocations at the lower cladding-guiding layer interface and the threading dislocation density in the Zn1−zCdzSe quantum well active region is about 107 cm−2. However, when lattice matched (to GaAs)ZnSySe1−y is used as the guiding layer the entire laser structure is pseudomorphic and the threading dislocation density is <106 cm−2. The combination of low defect density and enhanced carrier and optical confinement by using Zn1−xMgxSySe1−y quaternary cladding layers has produced significant improvement in the room temperature threshold current (500 A/cm2) and maximum operating temperature (394 K).

This paper reports on a new approach for reducing the threading dislocation density in GaAs on Si. We have used InxGa1-xAs/GaAs strained-layer superlattices (SLSs) grown on GaAs/Si at 300°C by migration-enhanced epitaxy as threading dislocation barriers. Different from conventional high-temperature-grown SLSs, the low-temperature-grown SLSs are only slightly relaxed by misfit dislocation formation at GaAs/SLS interfaces. Thus, considerable strain can be accumulated in SLS. In addition, new threading dislocation generation due to the misfit dislocation can be suppressed. These factors lead to effective threading dislocation bending and to significant reduction in the dislocation density. For the samples with a SLS of x=0.3, the average etch-pit density is 7×104 cm-2, which is the lowest value ever reported.