Reduction of delay variations in arithmetic circuits using a redundant representation

The speed of an adder is a significant factor in the performance for any arithmetic circuit. This paper primarily evaluates four different 4-bit adder architectures on 28nm technology in terms of speed. However, the performance of the adders is analysed based on delay, power dissipation, leakage current and area. The purpose of our work is to analyse the designs of the 4-bit adders, so as to give a better understanding as to which adder is suitable to the designer. The 4-bit adders, namely ripple carry adder (RCA), carry lookahead adder (CLA), carry skip adder (CSK) and Manchester carry chain adder (MCC), are designed using Cadence Virtuoso on 28nm technology. They are simulated and analysed at various supply voltages ranging from 0.6 to 1 V using ELDO tool. The results show that at 0.6 V CLA is faster than CSK by 27.9%, MCC by 8.2% and RCA by 26.46%.

Adders play a central role in arithmetic computations as well as digital signal processing. Besides addition, adders are used in multiple operations in processors. Based on our requirements upon variegated parameters our choice on adders can also be changed. Most digital systems, such as processors or computers, have 32-bit architecture, which includes 32-bit integers, registers, and memory locations, among other things. As a result, optimising 32-bit adders minimises total latency and thus enhances speed. In this work, performance analysis of 32-bit adders is compared by the Verilog programming language. 32-bit adder design is highly crucial as its architecture is widespread and used widely, and it is so hard to design. Designing several adders of 32 bit such as carry save adder (CSA), carry look ahead adder (CLA), ripple carry adder (RCA), modified carry select adder (MCSA), carry skip adder (CSKA), kogge stone adder (KSA) and carry select adder (CSLA), are explained in this work based on memory usage and delay. Discussions on adder types are made that aids in reducing the time usage on tedious tasks. CLA and CSKA were compared. Synthesis and simulation are done using Xilinx ISE tool. The simulation results help in the determination of the attributes that were assorted.

Adders are digital circuits that perform addition operation. There are various types of adder structures such as Ripple carry adder (RCA), carry look ahead adder (CLA) , carry select adder (CSLA) , carry save adder(CSA), carry skip adder, carry increment adder and so on. Again CSLA is of two types that is linear carry select adder (LCSLA) & square root carry select adder (SQRT CSLA). To design an efficient adder circuit in terms of area, power and speed is one of the challenging task in modern VLSI design field. In this paper performance analysis of different adder structures like RCA, CLA, LCSLA and SQRT CSLA has been carried out and then a Heterogeneous adder structure is proposed, which compose of four different sub homogeneous adders (RCA, CLA, LCSLA and SQRT CSLA). The heterogeneous adder structure is used to demonstrate the tradeoffs between the speed and area. In this paper, all adder structures i.e., RCA, CLA, LCSLA and SQRT CSLA are to be designed and are to be compared with each other in terms of delay and area. Then by using the homogeneous adder structures different heterogeneous adder structures of 16-bit size are to be designed. Different heterogeneous adder architectures are compared with each other in terms of delay (ns) and area (number of LUTs). All the adder structures are designed using VHDL with the help of ISE Xilinx design suite 14.2 and functionally simulated using ISIM simulator. All the designs are to be synthesized using Xilinx XST synthesizer.

We present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130 nm CMOS technology. At 1.2 V and 25 C, the 32-bit adder has a critical path delay of 921 ps and average power dissipation normalized to 600 MHz operation of 0.786 mW. We also present a technique to quickly perform saturating addition, which is useful in a variety of digital signal processing and multimedia applications. Our technique for fast saturation is based on techniques for carry select addition and works particularly well when the input and output operands can have different formats. A 40-bit carry skip adder that uses our technique for fast saturation has critical path delays of 1149 ps in 130 nm technology at 1.2 V and 25 C and 560 ps in 90nm technology at 1.0 V and 25 C. The 40-bit adder's average power dissipation normalized to 600 MHz operation is 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results. Keywords: Adders, Carry Bypass Adder (CBA), Carry Increment Adder (CIA), Carry Look-Ahead Adder (CLA), Carry Skip Adder (CSkA), Han Carlson Adder (HCA), Ripple Carry Adder (RCA)

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

The design of digital structures that are implemented in FPGAs or ASICs is subject to many constraints. This work proposes that systemic design should be used to optimize area/speed tradeoffs in simple digital structures (adders). Systemic approach in complex problem solving allows the analysis and synthesis of objects of different nature and complexity from a holistic point of view, considering the initial complex factors for each system. Although there are a variety of adder circuits (Ripple Carry Adder; Carry Skip Adder; Carry Increment Adder; Sklansky Adder; Kogge & Stone Adder), following the systemic design, optimum structures are obtained, given the initial complex constraints.

This paper compares several designs of spanning tree adders for 16 and 32 bit widths. The carry select part of the spanning tree is done using ripple carry and carry skip adders (4, 8 and 16 bits) and compared in terms of delay, complexity and power consumption. The spanning tree design is also compared with that of a conventional carry lookahead adder. All the designs are done using only 2 input NAND and NOR gates and inverters in 0.18 μm CMOS technology. The delay and power consumption is determined by use of simulations performed with Synopsys and Cadence design tools. The spanning tree adder realized with carry skip adders is about 40% faster than the carry lookahead adder with an approximate increase of 17% in complexity and 22% in power.

In this paper we present a fast radix-4 division algorithm for floating point numbers. This method is based on Svoboda's division algorithm and the radix-4 redundant number system. The algorithm involves a simple recurrence with carry-free addition and employs prescaling of the operands. In the proposed divider implementation, each radix-4 digit (belonging to set {-3,...,+3}) of the quotient and partial remainder is encoded using two radix-2 digits (belonging to the set {-1,0,+1}) and this leads to hardware simplicity. The quotient digits are determined by observing three most-significant radix-2 digits of the partial remainder and independent of the divisor. The architecture presented for the proposed algorithm is faster than previously proposed radix-4 dividers, which require at least four digits of the partial remainder to be observed to determine quotient digits. >

In recent years, there has been a lot of research into statistical static timing analysis (SSTA) to compute the critical path delay of a circuit under timing variation. In order to compute the true critical path delay, however, false paths that cannot be sensitized by any input vector must be identified first. Since SSTA is unable to capture the dynamic timing behavior of a circuit, it is completely blind to false paths, and thus it overestimates the circuit timing. In this paper, we propose a new concept of timing analysis approach called statistical dynamic timing analysis (SDTA), which is able to precisely express the statistical behavior of dynamic transitions at the output of gate into a compact form and to directly evaluate and propagate the expressions throughout the circuit, by which the false paths can be cleaned effectively. In addition, to be practical, we propose a couple of techniques that enable a fast computation of the SDTA. We tested the proposed approach on ISCAS benchmarks and carry skip adders under timing variation to show its accuracy in computing the distribution of the true critical path delay of a circuit. In summary, compared to the previous approach of false path-aware statistical timing analysis, our timing analysis technique is able to reduce the accuracy error in the mean and standard deviation of true critical path delay distribution from 9.8% to 1.9% and from 29.4% to -3.4%, respectively.

Adders are the most important fundamental blocks of the digital systems which are used in a wide variety of applications. Among them the first basic adder is the Ripple Carry Adder (RCA) and the fastest adder is the Carry Select Adder (CSA). Though all these adders are existed, the speed adding using low power and optimized area is still a challenging issue. In this paper a new technique, Modified Gate Diffusion Input (MOD-GDI) is used to achieve an optimized design with less transistor count and low power dissipation. In the proposed work the 8-bit, 16-bit Ripple Carry Adder and the 8-bit, 16-bit Carry Select Adder have been designed using the CMOS and MOD-GDI techniques. The comparison of their power dissipations and overall transistor count is done and proved that low power and optimized designs are achieved through MOD-GDI technique. The simulation is carried out using Mentor Graphics tool with a supply voltage of 1.8 V at 90 nm technology.

This paper describes a new type of carry-skip adder, which can be faster than the conventional two-level carry-skip adders. A way to design optimum adders of this new type is described. In optimum adders of this type, the sizes of the sections of bit positions are bimodal, but the sizes of the blocks in each section are unimodal, unlike the bimodal block sizes in Guyot et al.'s traditional two-level carry-skip adders. A 60-b 2- mu m CMOS adder of this type is designed. This adder's simulated delay is approximately 12.6 ns.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper proposes a square root hardware algorithm using the redundant binary representation in the internal computation. A discussion is made for the realization of a combinational square‐rooter based on the algorithm. This paper considers the computation of the mantissa in square‐rooting for the binary normalized floating‐point representation. The proposed algorithm is a kind of subtract‐and‐shift square‐root method. Partial remainders are represented by the redundant binary representation, where each digit is an element of {‐1, 0, 1}. Then each digit of the square root is determined from {‐1, 0, 1}, by examining the upper three digits of the partial remainder. The computation for the partial remainder is affected in the redundant binary number system. Finally, the square root determined in the redundant binary representation is converted into the ordinary binary representation. In the redundant binary representation, the addition of two numbers can be effected without carry propagation. Consequently, by using the combinational circuit, each digit of the square root can be determined in a constant time, independently of the number of digits of the operand. The computation time for the n‐bit square rooter (number of stages) is proportional to n. The number of logic elements in the circuit is proportional to n2. The hardware structure is a regular cellular array, which is suited for VLSI implementation. When the circuit is implemented on a VLSI chip, the chip is proportional to n2. The proposed square rooter has nearly the same circuit structure and the hardware complexity, compared with the conventional subtract‐and‐shift square rooter using ripple carry adder. The computation time is approximately one‐fifth for 32‐bit and one‐tenth for 64‐bit, compared with earlier circuits.

This paper presents the concept, traits, principle and structure of 64-bit high speed VLIW microprocessor. The microprocessor facilitates 16 kinds of operational function. Out of these, our main focus is on the add operation. The add operation is implemented using 64-bit adders namely, Carry Look-ahead Adder, Carry Select Adder, Ripple Carry Adder, Weinberger Adder, Ling Adder and Modified CSLA using Ling Adders. These different processor architectures are then compared for Delay. It is observed that the architecture with Modified CSLA using Ling Adder incorporated is the fastest. The design is implemented Xilinx Virtex-7 FPGA, xc7vx690tffg1761-2 device and is simulated, synthesized and implemented with the help of Xilinx Vivado 2015.4 using Verilog HDL.

Central processing unit (CPU) is the brain of the computer, and arithmetic and logic unit (ALU) serves as the major component of the CPU. In ALU, for the addition of multiple bits, ripple carry adder (RCA) with carry select adder (CSA) configuration is used in this paper. These configurations require various blocks of full adders in cascaded form leading to enhanced area of the circuit. Therefore, this paper mainly focuses on reducing the area of such adders, so that implementation of ALU can be done in minimum space. Here, the area of 4-bit and 8-bit adders with CSA is designed and optimized in such a way that adders can improve the area consumption. The designing of the proposed adder is implemented in Verilog hardware description language (HDL) and simulated using ISIM simulator. It is synthesized and implemented using Xilinx ISE 14.7 by selecting Spartan 3E family and XC3S100E as the device. The proposed 4-bit adder and 8-bit adder reduces the area by 16.8 and 7.38%, respectively.KeywordsArithmetic and logic unitCarry propagation delayRipple carry adderCarry select adder