Simulation technique for noise and timing jitter in phase locked loop

Timing jitter is a concern in high frequency oscillators; the presence of timing jitter will degrade system performance in many high speed applications. In the first part of the paper, the authors have simulated the timing jitter due to CMOS device noise in a nine-stage CMOS differential ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation results show that the variation of absolute jitter due to flicker noise has t-dependence while for white noise it has t/sup 0.5/-dependence; these are consistent with accepted theory. Two important parameters, cycle jitter and cycle-to-cycle jitter, used to describe jitter performance can be obtained from simulation. Simulation results are also compared with measurement results, and it is shown that simulation results are very close to measurement results. All these serve to verify the validity of this technique. In the second part of the paper, the authors have employed this methodology and investigated the timing jitter in silicon BJT/or SiGe HBT ECL ring oscillators, and they have shown that BJT/or SiGe HBT oscillators have lower jitter compared to their CMOS counterparts. The methodology described in the paper is also applicable to other types of clock generator and oscillators such as LC oscillators, as well as other kinds of noise source such as power supply and substrate noise.

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

The anti-jitter circuit (AJC) [1], [2]-[4] is able to reduce phase noise and spurious content of any frequency source at sideband frequencies above a defined cut-off frequency. By contrast, a phase-locked loop (PLL) can only reduce the intrinsic phase noise of its output oscillator closer to carrier lower than a defined cut-off frequency. The AJC has no output oscillator, but its phase noise performance can be assessed as if it had [5]. This paper reports the invention of the adiabatic AJC (AAJC) [6]-[8], giving the AJC improved power consumption, frequency range, and maximum frequency of operation. The term "adiabatic" is adopted to indicate that the core part of the new circuit does not require a power supply. It takes power from the input source directly to create the sawtooth waveform that has considerably reduced time jitter on the longer of its two ramp waveforms. Discrete models of the AJC are now operational at 30 MHz, which is twice the 15-MHz operation previously reported. The cut-off frequency of suppression has been maintained at a few kiloHertz. Noise analysis now shows performance comparable with an LC oscillator is possible. SPICE simulations show potential operation up to 5 GHz. The AAJC is also cascadable up to the intrinsic (shot) noise limit. Shot noise can be reduced by feedback.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

The reduction of timing jitter has become a primary goal in the design of Phase Locked Loops (PLLs) and Delay Locked loops (DLLs) for high data rate systems. Timing jitter causes a decrease in timing margin and reduces the maximum achievable frequency of operation for digital circuits. This paper proposes a capacitor compensation scheme to reduce accumulated jitter in PLLs. The focus of this investigation is on the reduction of power supply induced noise to the Voltage Controlled Oscillator (VCO). For a 250MHz PLL designed in 0.13um CMOS technology the long term accumulated jitter was simulated at 1.3ns peak to peak which reduced to 750ps peak to peak after the addition of our compensation scheme.

The phase locked loop (PLL) is a control system that compares the phase of the output signal with that of the input signal and proportionally varies its output based on the phase difference between them. PLL most prolifically finds its applications in frequency generation, clock and data recovery, carrier frequency generation in modulation and demodulation, frequency synthesizers, jitter and skew reduction, and many more. Mixed-signal and digital circuits employ PLL for clock generation to get the synchronous transactions with the clock. So it is mandatory to properly design the PLL to obtain minimum jitter on the clock edges. The PLL designed in this work was based on the famous charge-pump (CP) architecture and was implemented using the semiconductor laboratory (SCL) 180 nm technology in Cadence Virtuoso. This work uses NOR-based PFD using TSPC latches, Transmission gate CP, Current Starved VCO, and TSPC-based divider circuit. The proposed model of PLL has phase noise of the PLL as −113 dBc/Hz, the power consumption of the total PLL as 3.2 mW at 1.8 V power supply with deterministic jitter of about 5.62 ps and the settling time of the control voltage as 850 ns.

This work investigates the influence of the output power of a spin torque oscillator (STO) on the operation of a phase locked loop (PLL) circuit. Timing jitter and minimum output power for stable PLL operation determined by Johnson noise and shot noise are first theoretically calculated, and compared with experimental results. The theory and experiment show a reasonably good agreement, indicating that smaller than −50 dBm (10 nW), or −60 dBm (1 nW) when a low pass filter is used, of output power is sufficient for stable PLL operation if a large timing jitter is acceptable. However, it is also shown that a large output power is needed to suppress timing jitter down to the level comparable to state-of-the-art commercial PLL circuits. The estimate of minimum output power for stable PLL operation is verified by intentionally attenuating the STO output signal down to −55 dBm (3.2 nW) and demonstrating a stable phase locked oscillation.

A new low-cost technique for jitter measurement of phase-locked loops (PLLs) is described. The proposed technique can be applied to PLLs whose jitter is predominantly due to power supply noise. Accurate measurement of jitter to picosecond accuracy using conventional methods requires very high-cost tester instrumentation. By modulating the supply voltage to the PLL and noting that PLL jitter is extremely sensitive to power supply variations, it is possible to introduce significant jitter into the PLL output which can be measured using a low-cost tester During production test, a regression model is used to predict the inherent PLL jitter from the measurement of power supply induced jitter.

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

Radio frequency (RF) receivers are common in many modern communications and radar systems, and they suffer from many performance degradation factors due to hardware limitations. Among all performance degradation contributors, phase noise and time jitter are particularly troublesome since they cause random errors which are difficult to compensate. The local oscillator in the receiver front end is a major contributor of phase noise, while the analog-to-digital converter (ADC) introduces time jitter. It is desired to know the accumulated effect of individual phase noise sources and time jitter. The total effect of all phase noise and jitter can be represented by an accumulated phase noise term at the ADC's output, called total phase noise (TPN) in this brief. The focus of this work is on measuring and modeling TPN in the RF receiver by applying optimization techniques. In contrast to traditional phase noise measurement that typically requires a high-quality tunable downconverter, a digital approach using the data captured directly by the RF receiver is proposed. In addition, iterative optimization-based TPN spectral model fitting and statistic modeling are introduced. The model is examined using the measured TPN. It is confirmed that the RF receiver TPN can be viewed as a wide-sense stationary zero-mean Gaussian process with certain spectral profile.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98dBc/Hz. The locking range of the PLL is from 22.6GHz to 23.3GHz and the reference spur level is -69dBm that is 54dB bellow the carrier. The power consumption is 9.2mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

This paper presents a high-speed, broadband phase -locked loop (PLL) for RF transceiver in 65nm CMOS process. Programmable structures are used to improve the lock speed of the PLL, the charge pump and loop filter can be adjusted by digital bit to reduce locked time of PLL. An integrated voltage-control oscillator (VCO) with 75% tuning range and a high-speed divider are used to accomplish all the frequencies. To achieve a wide tuning range while keep a low gain and a low phase noise, the VCO uses switched capacitor array. Finally, the PLL realizes 6-12 GHz wide frequency coverage. The phase noise performance at 6GHz is -113dBc/Hz@lMHz. The layout area is only 0.5265mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Working at 1. 2V supply voltage, the power consumption of the circuit is 11.3432 mW. The lock time of the PLL after using AFC is about 15. 258us.