Stability analysis for the high-order leapfrog sigma-delta A/D converters

A low power second order hybrid loopfilter Sigma-Delta modulator with high resolution is presented. The structure is composed by a first active integrator followed by a switched-capacitor (SC) integrator. This modulator architecture exploits the coefficient scaling property of the active integrator, while the SC integrator is modified to shift its pole from inside the unit circle to z=1 at DC in the z-domain. Poles of the loopfilter are zeroes of the noise transfer function (NTF). As a result the NTF zero is also shifted to z=1. This NTF zero compensation for the SC integrator will result in better in-band noise suppression & improved noise shaping. The second order hybrid sigma-delta modulator with a 4-bit quantizer and an oversampling ratio (OSR) of 32 is simulated in simulink. The modulator can achieve 89dB SNDR with a dynamic range of 91dB.

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved.

This paper presents the system-level design and behavioural implementation of a second-order continuous-time (CT)sigma-delta modulator for high-resolution, low-frequency sensing applications. The modulator architecture is synthesized using the MATLAB Delta-Sigma Toolbox and implemented behaviorally in Cadence Virtuoso using Verilog-A models. A cascade of integrators feed-forward (CIFF) architecture with a 1-bit quantizer and an oversampling ratio (OSR) of 12 is employed to achieve high resolution while maintaining stability. The discrete-time noise transfer function (NTF) is transformed to its continuous-time equivalent using the impulseinvariant transformation with an NRZ feedback DAC pulse. Simulation results demonstrate practical second-order noise shaping. For a 900 mV, 1 Hz sinusoidal input, the modulator achieves an SNR of 86dB, corresponding to an effective number of bits (ENOB) of 14 bits. The influence of the integrator's finite DC gain and limited gainbandwidth product (GBW) on performance is also evaluated. The results validate the proposed modulator architecture for precision low-bandwidth sensing front-end applications.

This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive approximation register (SAR) ADC that dynamically updates the references for the post-stage single-bit second-order delta-sigma modulator to obtain a higher resolution with lower power. The sampling rate of the proposed ADC can be configured to be 1.6, 3.2, 6.4 and 10-MS/s such that four resolution modes, including 12, 14, 16 and 18-bit, can be provided accordingly. Note that pole locations of the noise transfer function (NTF) vary with different OSR's, and noise-shaping effect, together with the power efficiency, can be degraded. To solve this issue, the pole-optimization technique is proposed in this paper. In this way can the pole locations be reconfigured according to the specific OSR. Additionally, the bandwidths of the operational amplifiers are also modulated in different oversampling ratio (OSR) scenarios to further improve the energy efficiency. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, the prototype occupies 1.01 mm2. On condition of an OSR of 250, the proposed ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 102.8 dB, while dissipating 1.3 mW.

The performance of a sigma-delta analog-to-digital converter (ADC) critically depends on one or more of the main three parameters: over-sampling ratio, the order of the modulators, and the number of bits used. Increasing each one of these parameters presents a degree of challenge (i.e., the increase in the over-sampling ratio is limited by the technology and the power consumption requirement). This paper presents a method to obtain high order noise shaping with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -path architectures that are based on first-order or second-order modulators. The desired noise transfer function (NTF) is obtained by suitable cross-coupling paths. The method was applied to a two-path first-order modulator for obtaining a second-order noise shaping. The performances of the proposed sigma-delta ADC were verified at the behavioral and transistor level implemented in 90-nm CMOS technology.

A new fully passive noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs) was proposed. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. The additional pole increases the efficiency of noise shaping to further 3 dB. So, the use of higher over sampling ratios (OSR) and increased effective number of bits (ENOB) is possible. The architecture was applied to the design of a 9.8-bit ENOB SAR ADC in a 65 nm complementary metal-oxide semiconductor (CMOS) of United Microelectronics Corporation (UMC) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architecture provides 3.8 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

This paper presents an elaborate plan and optimization method for designing and implementing low-order band pass digital sigma-delta modulator with high order output dynamic range (DR). The noise suppression in the pass band region of the modulator and high order output DR would be achieved by designing and optimizing the Noise Transfer Function (NTF) based on over sampling ratio (OSR) and desired modulator operational frequency and designing the Signal Transfer Function (STF) by the mean which the optimum gain in desired frequency would be acquired. Designed and optimized modulator has been implemented completely on digital circuits and it would be shown that the first order designed modulator has the output dynamic range of 90dB which corresponds to 15 bits data conversion. Results from various simulations illustrate both the stability and high performance of the design and flexibility of the overall structure.

Sigma-Delta modulators (SDMs) are capable of shaping the quantization noise out of a specific frequency band defined by their noise transfer function (NTF). A single-bit output SDM pose further advantages in applications that would typically require a multi-bit DAC, since then only a single-bit DAC is required, which is much easier to design and is inherently linear in comparison to a multi-bit one. Look-ahead SDMs have been proposed to enhance the signal-to-noise-and-distortion-ratio (SNDR) and the output bandwidth of conventional single-bit SDMs. Multi-Step Look-Ahead sigma-delta modulators (MSLA SDMs) further reduce the hardware complexity required for the implementation of typical look-ahead SDMs while maintaining their performance advantages. In this work the architecture and the benefits of the MSLA SDMs are showcased. Finally the advantages of the MSLA SDMs over single-bit conventional ones are demonstrated and several hardware implementation choices for design optimization are discussed.

&lt;p&gt;This paper presents methodologies for suppressing the spatial and the temporal noise in a CMOS image sensor (CIS). First of all, it demonstrates by using a longer-length column bias transistor, both the fixed pattern noise (FPN) and temporal noise can be suppressed. Meantime, it employs column-level oversampling delta-sigma ADCs to suppress temporal noise as well as to facilitate the realization of the thermal compensation of dark signal non-uniformity (DSNU). In addition, the image pixels are re-configured as temperature sensors with inaccuracies within ±0.65 °C, between -20 and 80 °C. If the dark current and its non-uniformities are caused by thermal gradients, the obtained in-pixel thermal information can be employed to compensate for the measured dark current by 95 % and DSNU, up to 13 %. All the column-level 13 bit 2 &lt;sup&gt;nd&lt;/sup&gt;-order incremental delta-sigma ADCs are measured with SNR around 65 dB and INL around 1.5 LSB, when tested with a -8 dB input signal and sampling at 2 MHz with an oversampling ratio (OSR) of 128, when the full scale voltage is 2 Vp-p. The 4T Pinned Photodiode (PPD) CIS is measured to have a temporal noise of 34~\\mu \\text{V} rms (with an OSR of 128, or, an input referred temporal noise of 0.5 e &lt;sup&gt;-&lt;/sup&gt; rms, with a conversion gain, CG, of 73~\\mu \\text{V}/ \\text{e}^{-} ), a column gain FPN of 0.06 %, a dynamic range (DR) of 92 dB (with OSR = 512), as well as a linearity of 1 %. It has a measured DSNU of 3.2 %, after the thermal compensation using the in-pixel temperature sensors, a dark current of 290 pA/cm &lt;sup&gt;2&lt;/sup&gt; and 15 pA/cm &lt;sup&gt;2&lt;/sup&gt;, measured at 60 °C, before and after the thermal compensation, respectively. &lt;/p&gt;

This brief presents a power reduction technique for continuous time sigma–delta modulators (CTSDMs). The approach consists of two elements. First, a passive low-pass filter is added in front of the modulator’s loop filter to reduce the high frequency components in the loop. As a result, the slew rate requirements of the opamps can be greatly reduced which allows a significant power saving. Unfortunately, the insertion of this low-pass filter also changes the modulator’s loop gain, and hence affects the noise transfer functions (NTFs) and signal transfer functions (STFs), in an undesired way. Therefore, the second proposed element consists of inserting a compensation branch which is such that the original loop gain, NTF and STF are restored. Thanks to this, our power saving technique is completely transparent on the system level such that all established techniques and toolboxes for CTSDM design can still be used. The technique is especially suited for one-bit CTSDMs, where the amount of high-frequency components in the loop is excessive. To showcase the technique, a self-oscillating sigma–delta modulator (which is a dedicated type of one-bit CTSDM) was implemented in a 65-nm CMOS process. It achieves a peak signal to noise and distortion ratio of 63 dB over a 20-MHz bandwidth at a power consumption of 1.7 mW while occupying a very small chip area of only 0.009 mm2.

This paper presents a low-distortion sigma-delta (Σ-Δ) ADC for micro-machined inertial sensors. The design adopts a single-loop, fourth-order low-pass single-bit modulator with feedforward paths which can ensure the signal transfer lossless and reduce the nonlinearity and power consumption. The chip is manufactured in standard 0.5µm CMOS process, and the area is 2.2mm2. The ADC achieves 108dB signal to noise ratio (SNR) and 110dB dynamic range (DR). Total power consumption is less than 15mW with 5V supply.

It is well known that /spl Sigma/-/spl Delta/ A/D converters having complementary signal and noise transfer functions exhibit high signal-to-quantization-noise ratios (SQNRs) and high dynamic ranges (DRs), but that they tend to be overly sensitive to capacitor mismatches (potentially leading to unstable converter operation) in a corresponding switched-capacitor (SC) hardware implementation. Recently, a new class of /spl Sigma/-/spl Delta/ A/D converters was developed based on magnitude-squared or magnitude complementary signal and noise transfer functions to decrease the sensitivity to capacitor mismatches at the expense of slightly lower SQNRs and DRs. This paper is concerned with the development of a novel approach to the design of /spl Sigma/-/spl Delta/ A/D converters. This approach combines the transfer function complementarity (in the overall frequency band) with signal and noise transfer function magnitude complementarity (in the signal passband) to obtain a single /spl Sigma/-/spl Delta/ A/D converter with a cascade-of-resonators configuration. Consequently, the resulting A/D converters achieve not only high-stability (arising from magnitude complementarity), but also high DR and SQNR (arising from transfer function complementarity) in the SC hardware implementation. A practical application example is given to illustrate the results.

A delta-sigma modulator (DSM) is proposed for the direct connection to micro-electro-mechanical systems (MEMS) microphone. To reduce power, both the DAC reference voltage (VREF) and the DSM supply voltage (VDD) are reduced to 700 mV by limiting the maximum linear acoustic input range to 110 dB SPL (sound pressure level). For the low VDD operation, the switched capacitor (SC) integrators of DSM employ CMOS inverters as amplifiers. A unity-gain buffer compensates the pole error of the SC integrator; it reduces chip area by replacing the auto-zero capacitor of conventional inverter-based SC integrator. Compared to the conventional integrator, the integrator of this brief reduces the pole error from 0.3% to 0.06%, reduces the chip area and the power by 32.4% and 24.8%, respectively. The 3rd order DSM in a 65 nm CMOS process was measured to have Walden-figure of merit (FoMw) 89.3fJ/step, dynamic range (DR) 90.1 dB, signal-to-noise ratio (SNR) 87.2 dB, signal-to-noise and distortion ratio (SNDR) 86.4 dB, and power 122 uW at 10 MHz clock frequency (Fs).

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

This paper presents a band-pass noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with a second-order modulator which is comprised of a fully passive switched-capacitor (SC) filter and a gain-boosted dynamic amplifier. It employs the error-feedback (EF) structure in a simple method to implement the complicated noise transfer function (NTF) zeros, which enhances the noise-shaping capability by minimally modifying a standard SAR ADC. Designed in 28 nm CMOS process, the prototype of proposed NS-SAR ADC achieves 76.84 dB signal-to-noise and distortion ratio (SNDR) with the bandwidth between 20 and 40 MHz and the FoMw is only 2.24 fJ/step at the oversampling ratio (OSR) of 5.