The Maximum Disjoint Routing Problem

The rapid development of information and communication technologies has driven the rapid growth of data traffic and the large requirement of high-speed optical transceiver modules. Usually, optical subassemblies through flexible printed circuit boards (PCBs) connect with the hard PCBs to compose as optical transceiver modules. Because of the impedance mismatch of connection between flexible PCB and hard PCB, the operation bandwidth of the module can be limited. In this paper, the design of connection between flexible PCB and hard PCB in optical subassembly modules will be investigated for increasing the operation speed of the module. First, the transmission bandwidth of flexible PCB is analyzed. High-frequency performances of three transmission line structures, micro-strip line, grounded coplanar waveguide, and top ground micro-strip line, are investigated in flexible PCB. High-frequency performances of flexible PCB with different bending types are also investigated. The flexible PCB has been verified to be suitable to use in 25 Gb/s applications. Next, the high-speed transmission performance is analyzed through the connection between flexible PCB and hard PCB, because the impedance mismatch usually occurs at the connection. The ground pads are added near the signal line of flexible PCB, and the ground pads are connected to the ground layer in PCB through ground vias. The anti-pad in hard PCB is added under the signal solder pad. The dip of S21 response can be eliminated by the optimized ground pad. The impedance mismatch can be reduced by the optimized anti-pad, the impedance increases from 40-Ω to 49-Ω at the connection between flexible PCB and hard PCB, and the transmission bandwidth can increase from 16.5 GHz to 23.5 GHz. TO-46 header is a common and low-cost packaging solution for DFB laser and photodiodes. The connection between flexible PCB and TO-46 header is also investigated. While the connection has a gap, the dip of frequency response will occur at lower frequency. While the connection is very close, the bandwidth can be larger than 25 GHz. The flexible PCB, hard PCB, and TO-46 header are combined together, and the 23 GHz transmission bandwidth can be obtained. The 25 Gb/s transmission eye diagram is also measured, and the eye height, rise time, fall time, and Q-factor are 268.14 mV, 13.78 ps, 13.56 ps, and 8.76, respectively. The combined flexible PCB, hard PCB, and TO-46 header are verified to be suitable to apply in 25 Gb/s optical subassembly modules, and will be able to be used in 100G Ethernet.

Longest‐path routing problems, which can arise in the design of high‐performance printed circuit boards (PCBs), have been proven to be NP‐hard. In this article, we propose a constraint programming (CP) formulation and a mixed integer linear programming (MILP) formulation to gridded longest‐path routing problems; each of which may contain obstacles. After a longest‐path routing problem has been transformed into a CP problem, a CP solver can be used to find optimal solutions. On the other hand, parallel MILP solvers can be used to find optimal solutions after the longest‐path routing problem has been transformed into an MILP problem. Also, suboptimal solutions can be generated in exchange for reduced execution time. The proposed formulation methods can also be used to solve shortest‐path routing problems. Experimental results show that more than 3,700x speed‐up can be achieved by using a parallel MILP solver with 16 threads in solving formulated longest‐path routing problems. The execution time can be further reduced if a computer containing more processer cores is available.

In this paper, we consider a routing problem for a single grasp-and-delivery robot used on a printed circuit (PC) board assembly line. The robot arranges n identical pins from their current configuration to the next required configuration by transferring them one by one in a transition. The n pins support a PC board from underneath to prevent it from overbending as an automated manipulator embeds electronic parts in the PC board from above. Each PC board has its own circuit pattern, and required configurations for PC boards all differ. Given an initial configuration of n pins and a sequence of m required configurations, the problem asks to find a transfer route of the robot that minimizes the route length over all m transitions. By applying a weighted matroid intersection algorithm, we show the repetitive routing problem to be 2-approximable in polynomial time.

This paper discusses a new route optimization for inspecting printed circuit boards (PCBs). In inspections of PCBs, a number of PCBs arrayed on a plane are tested by a probe in some order or sequence. Since the length of an inspection route depends on the order or sequence that the probe visits and tests each of PCBs, the finding of best visiting order or sequence is quite important in order to reduce the PCB inspection time. Recently, due to the miniaturization of PCBs, the procedure of “alignment” has become necessary before the electrical test, which means that there is a precedence constraint between alignment and test. This paper models a PCB inspection route optimization problem with alignment operations as a class of pickup and delivery traveling salesman problem (PDTSP) which is a mixed 0–1 integer programming problem. An efficient heuristic algorithm is proposed to solve the problem with a practical computational time. The proposed algorithm is installed into real PCB inspection machines that have been widely used in the world. Cost reduction effects for PCB inspection factories are discussed.

The frequency at the peak of electromagnetic radiation from a PCB (Printed Circuit Board) as a result of ground bounce is considered predictable from the frequency characteristics of the input impedance between the power supply and ground layer (below called the PCB impedance). However, the relationship is largely unknown. In this paper, the electromagnetic radiation of the PCB and the frequency spectrum of the PCB impedance are analyzed by the FDTD (Finite‐Difference Time‐Domain) method and their relational mechanism is studied by comparison with the measured values. It is found that the peak of the electromagnetic radiation appears at the frequency where the PCB is a minimum if the PCB is excited by a voltage source with an internal resistance sufficiently smaller than the PCB impedance, and that this peak is shifted toward the frequency at which the PCB impedance becomes a maximum if the internal resistance is increased. The radiation power ratio derived from the resistive components (called the resonant resistances) at two frequencies where the PCB impedance is maximum and minimum (resonant frequencies) mostly agrees with the ratio of the squares of the radiated electric field. Hence, the radiation peak frequencies of the PCB are determined both by the internal resistance of the excitation source and the resonant resistance of the PCB impedance. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 87(11): 30–38, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.10209

The research object in the work is the printed circuit boards (PCB) Production technological process using the additive technology of photopolymer 3D printing. The existing problem is that the manufacturing process of single-sided and double-sided PCBs, simple in technology, from the third to the fifth accuracy class, requires the use of a large amount of consumables and technological equipment. In turn, this affects the cost of the product. The research subject is models and methods for manufacturing PCB using photopolymer 3D printing. In order to reduce the cost of materials: film or aerosol photoresist, as well as reduce the number of technological operations, applying photoresist and for the manufacture of PCBs stencils, it is proposed to use photopolymer 3D printing technologies for the manufacture of PCBs. The paper analyzes the costs of Plexiwire Resin Basic Orange Transparen photopolymer resin for the manufacture of single-sided PCBs and calculates the cost of the consumable (resin) compared to the costs of dry film photoresist. 60 % cost of consumables (photopolymer resin) compared to dry film photoresist for making single-sided PCBs. The work is aimed at determining the dependence of the geometric dimensions of the PСВs topology and the consumption of photopolymer resin on the technological parameters of photopolymer exposure. A regression correlation model of the dependence of resin consumption on exposure parameters has been developed and correlation coefficients have been calculated. It has been established that with an increase in the exposure time of the photopolymer resin, the consumption of the photopolymer resin increases and the deviation of the geometric dimensions of the PCBs topology increases, which in turn negatively affects the quality of the product. Therefore, using the obtained regression model, it is possible to calculate the influence of parameters on the PCB topology and reduce the deviation of conductor sizes and resin consumption.

The printed circuit board (PCB) routing problem has been studied extensively in recent years. Due to continually growing net/pin counts, extremely high pin density, and unique physical constraints, the manual routing of PCBs has become a time-consuming task to reach design closure. Previous works break down the problem into escape routing and area routing and focus on these problems separately. However, there is always a gap between these two problems requiring a massive amount of human efforts to fine-tune the algorithms back and forth. Besides, previous works of area routing mainly focus on routing between escaping routed ball-grid-array (BGA) packages. Nevertheless, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. To mitigate the deficiencies of previous works, we propose a full-board routing algorithm that can handle multiple real-world complicated constraints to facilitate the printed circuit board routing and produce high-quality manufacturable layouts. Experimental results show that our algorithm is effective and efficient. Specifically, for all given test cases, our router can achieve 100% routability without any design rule violation while the other two state-of-the-art routers fail to complete the routing for some test cases and incur design rule violations.

Circuit design plays an essential role in all consumer electronics products. Printed circuit board (PCB) and very-largescale integration (VLSI) circuit designing requires optimization of the electronic components placement and wire routing to connect the components. Currently, circuit routing processes have been performed manually by experts, which greatly increases the cost of human resources and time. Such heuristic circuit designs are not optimized and may have errors, which is why automated circuit routing algorithms are important. However, it is difficult to obtain an optimal solution in circuit routing as it is an NPhard problem. In addition, poor circuit routing increases the wire length of the circuit, which causes an increase in circuit cost and weight as well as performance degradation. In order to achieve routing optimization, many technologies have been proposed, in which some have applied artificial intelligence (AI) to improve the overall performance and reduce the designing time. Accordingly, in this paper, routing problems in PCB and VLSI are explained, and proposed technologies to solve these routing problems are introduced. Especially, a detailed investigation and analysis of AI technologies grafted into circuit routing algorithms are explained, and the considerations for AI-based routing algorithms are presented.

This paper introduces a multi-terminal escape routing algorithm for the design of Printed Circuit Boards (PCBs) that control Digital Microfluidic Biochips (DMFBs). The new algorithm is based on the principle of negotiated congestion, which has been applied in the past to problems including FPGA routing and PCB escape routing for single-terminal nets. PCBs designed for Pin-constrained DMFBs, in which one control pin may drive multiple electrodes, require multi-terminal escape routing solutions. Experimental results indicate that negotiated congestion is more effective for multi-terminal escape routing than existing techniques, which are based on maze routing coupled with rip-up and re-route, yielding an overall reduction in the number of PCB layers in most the test cases that were tried.

Printed Circuit Boards (PCBs) are widely used in most electronic devices. Typically, a PCB design has a set of components that needs to be assembled. In a broad sense, this assembly task involves placing PCB components at designated location on a PCB board; fixing PCB components; and testing the PCB after assembly operation to ensure that it is in proper working order. The stringent requirements of having a higher component density on PCBs, a shorter assembly time, and a more reliable product prompt manufacturers to automate the process of PCB assembly. Frequently, a few placement machines may work together to form an assembly line. Thus, the application of more than one machine for component placement on a PCB presents a line-balancing problem, which is basically concerned with balancing the workload of all the machines in an assembly line. This paper describes the application of a new artificial intelligence technique known as the immune algorithm to PCB component placement as well as the line balancing of PCB assembly line. It also includes an overview of PCB assembly and an outline of the assembly line balancing problem. Two case studies are used to validate the IA engine developed in this work. The details of IA, the IA engine and the case studies are presented.

Defect inspection is essential in the semiconductor industry to fabricate printed circuit boards (PCBs) with minimum defect rates. However, conventional inspection systems are labor-intensive and time-consuming. In this study, a semi-supervised learning (SSL)-based model called PCB_SS was developed. It was trained using labeled and unlabeled images under two different augmentations. Training and test PCB images were acquired using automatic final vision inspection systems. The PCB_SS model outperformed a completely supervised model trained using only labeled images (PCB_FS). The performance of the PCB_SS model was more robust than that of the PCB_FS model when the number of labeled data is limited or comprises incorrectly labeled data. In an error-resilience test, the proposed PCB_SS model maintained stable accuracy (error increment of less than 0.5%, compared with 4% for PCB_FS) for noisy training data (with as much as 9.0% of the data labeled incorrectly). The proposed model also showed superior performance when comparing machine-learning and deep-learning classifiers. The unlabeled data utilized in the PCB_SS model helped with the generalization of the deep-learning model and improved its performance for PCB defect detection. Thus, the proposed method alleviates the burden of the manual labeling process and provides a rapid and accurate automatic classifier for PCB inspections.

A reliable and accurate analytical model is desired for the printed circuit board (PCB) with IC package to predict the system response due to loadings such as shock and vibration simulation or even with thermal effect. This work addresses the procedure of model verification by the adoption of experimental modal analysis (EMA) to validate the finite element (FE) model constructed by FE commercial software. The PCB with one package adhered with the heating pad to emulate the heat effect is first considered for completely free boundary condition. The refined FE model of the PCB consists of detail components, such as the chip, substrate, compound and solder balls. The thermal effect on the PCB is simulated to conduct the temperature field analysis as well as the thermal stress. The modal analysis on the PCB with the heating in steady state is then performed to obtain the structural modal parameters, i.e. natural frequencies and mode shapes. The EMA is also carried out to determine the system modal properties that are used to update the analytical FE model. Through the comparison of frequency response functions and modal parameters between the analytical FE model and the real PCB structure, the refined FE model can be verified for material properties and thermal boundary conditions. The same procedure for model verification is then conducted via both EMA and FEA on the PCB in the fixed boundary that complies with the test fixture for the random vibration test of JEDEC specification. The verified equivalent FE model of the PCB can then be adopted to perform spectrum response analysis accordingly.

Printed circuit boards (PCBs) are designed for packing two or more semiconductor chips. On these PCBs, there are various types of faults in the wiring. We must therefore test the PCBs to detect these faults, and it is essential to establish an efficient testing method. One type of test method uses two probes. Two probes, each touching one edge (end) of an inter-chip wiring, are used to check for the presence of faults. Testing is complete when we have confirmed that no faults exist on the PCB. The objective is to minimize the completion time for the testing, that is, our aim is to design efficient routes for the two probes; this is a two-probe routing problem. Several previous studies have proposed an approach involving a two-phase method. Although the two-phase method quickly finds a feasible solution, there is no guarantee that the solution is good. Besides, in recent years, PCB technology provides dense assembly capability and increased chip packaging; this implies that the scale of the two-probe routing problem becomes larger and the problem is difficult to be solved. We therefore propose a new approach, where we formulate a two-probe routing problem as a combinatorial optimization problem and then, we solve the combinatorial optimization problem by using genetic algorithm.We expect that our approach is useful for solving the large-scale problems. In computational experiments, we compare the results of our approach with those obtained using the two-phase method, and we show that our approach outperforms the two-phase method.

In this paper, we consider a repetitive routing problem which we find on a printed circuit board assembly line. There are m different printed circuit boards to be processed. As an automated manipulator embeds electronic parts in a printed circuit board from above, n identical pins from underneath protect it against overbending. A dedicated pin configuration is designed for each printed circuit board so that pins do not obstruct its own circuit. A single grasp-and-delivery robot transfers the pins one by one to arrange them from a configuration to another one. Given an initial configuration of pins and a permutable set of m required configurations, our repetitive routing problem asks to find a configuration sequence, i.e., a processing order of m printed circuit boards, and a transfer route of the grasp-and-delivery robot so that the route length over all m transitions is minimized. We first design a polynomial time approximation algorithm with factor four to a restricted version of the repetitive routing problem with a non-permutable set of configurations, i.e., with a fixed processing order of m printed circuit boards. Applying the procedure, we then show that the repetitive routing problem with a permutable set of configurations admits a polynomial time approximation algorithm with factor six.

A printed circuit board (PCB) is an essential element for practical circuit applications and its failure can inflict large financial costs and even safety concerns, especially if the PCB failure occurs prematurely and unexpectedly. Understanding the failure modes and even the failure mechanisms of a PCB failure are not sufficient to ensure the same failure will not occur again in subsequent operations with different batches of PCBs. The identification of the root cause is crucial to prevent the reoccurrence of the same failure. In this work, a step-by-step approach from customer returned and inventory reproduced boards to the root cause identification is described for an actual industry case where the failure is a PCB burn-out. The failure mechanism is found to be a conductive anodic filament (CAF) even though the PCB is CAF-resistant. The root cause is due to PCB de-penalization. A reliability verification to assure the effectiveness of the corrective action according to the identified root cause is shown to complete the case study. This work shows that a CAF-resistant PCB does not necessarily guarantee no CAF and PCB processes can render its CAF resistance ineffective.