Using constraint geometry to determine maximum rate pipeline clocking

With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of authentic chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme, where all combinational blocks function within one clock period, so that a netlist of combinational logic gates and flip-flops is sufficient to duplicate a design. In this article, we propose to invalidate the assumption that a netlist completely represents the function of a circuit with unconventional timing. With the introduced wave-pipelining (WP) paths, attackers have to capture gate and interconnect delays during reverse engineering, or to test a huge number of combinational paths to identify the WP paths. To hinder the test-based attack, we construct false paths with WP to increase the counterfeiting challenge. The experimental results confirm that WP true paths and false paths can be constructed in benchmark circuits successfully with only a negligible cost, thus thwarting the potential attack techniques.

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. E. I. Boemo, S. López-Buedo, and J. M. Meneses, "Some experiments about wave pipelining on FPGA's", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 6, n. 2, p. 232 - 237

This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is developed. In order to minimize the clock period of level-sensitive circuits, the simultaneous effects of time borrowing and nonzero clock skew scheduling are considered. The clock period minimization problem is formulated for both single-phase and multi-phase clocking schemes. The ISCAS'89 benchmark circuits are used to derive experimental results. LP minimization problems for these benchmark circuits are generated using the modified big M (MBM) method and the generated problems are solved using the industrial LP solver CPLEX . The experimental results demonstrate up to 63% improvements in minimum clock period compared to flip-flop based circuits with zero clock skew.

In spite of recent advances in circuit retiming theory, especially for circuits that use level-sensitive latches, automatic retiming tools see relatively little use in practice. We suggest that the reason for the poor results reported for retiming is that it has been applied too late in the design process when there is little flexibility for performance improvement. We give an example of using retiming early in the design process to achieve better performance while at the same time simplifying the design process itself. We extend the circuit model to include clock skew, latch propagation delay, setup and hold parameters which allow retiming to generate the fastest circuit subject to a given amount of clock stew, or generate the most robust circuit with respect to skew for a given clock frequency. We illustrate these techniques using a serial-parallel multiplier circuit and show that while edge-clocked circuits require a speed margin for clock skew, level-clocked circuits can be retimed to be inherently skew-tolerant.

Wave pipelining is a method of speeding up the circuit design without the insertion of registers. This reduces the overhead related to clocking significantly and allows for better temporal logic utilization. However, because of the fact there are no intermediate registers, the clocking of wave pipelined circuits becomes more delicate and very susceptible to delay changes due to process, voltage and temperature (PVT) variations. With the traditional method of pipelining, it becomes just a problem of frequency adjustment, but, with wave pipelining, it becomes a more difficult problem due to more complicated constraints involving clock frequency and skew. In this paper, we look at some of the prior works done in this area, and introduce a localized clock circuitry scheme to address this issue.

Pulsed latches, latches driven by a brief clock pulse, offer the convenience of flip-flop-like timing verification and optimization, while retaining superior design parameters of latches over flip-flops. But, pulsed latch-based design using a single pulse width has a limitation in reducing clock period. The limitation still exists even if clock skew scheduling is employed, since the amount of skew that can be assigned is practically limited due to process variations. The problem of allocating pulse width (out of discrete number of predefined widths) and scheduling clock skew (within prescribed upper bound) is formulated, for the first time, for optimizing pulsed latch-based sequential circuits. An allocation algorithm called PWCS_Optimize is proposed to solve the problem. Experiments with 65-nm technology demonstrate that small number of variety of pulse widths (up to 5) combined with clock skews (up to 10% of clock period) yield minimum clock period for many benchmark circuits. The design flow including PWCS_Optimize, placement and routing, and synthesis of local and global clock trees is presented and assessed with example circuits.

This paper proposes an efficient algorithm for automatic and optimal tuning of pulse amplitude and width for sequential parameter estimation (SPE) of the neural membrane time constant and input-output (IO) curve parameters in closed-loop electromyography-guided (EMG-guided) controllable transcranial magnetic stimulation (cTMS). The proposed SPE is performed by administering a train of optimally tuned TMS pulses and updating the estimations until a stopping rule is satisfied or the maximum number of pulses is reached. The pulse amplitude is computed by the Fisher information maximization. The pulse width is chosen by maximizing a normalized depolarization factor, which is defined to separate the optimization and tuning of the pulse amplitude and width. The normalized depolarization factor maximization identifies the critical pulse width, which is an important parameter in the identifiability analysis, without any prior neurophysiological or anatomical knowledge of the neural membrane. The effectiveness of the proposed algorithm is evaluated through simulation. The results confirm satisfactory estimation of the membrane time constant and IO curve parameters for the simulation case. By defining the stopping rule based on the satisfaction of the convergence criterion with tolerance of 0.01 for 5 consecutive times for all parameters, the IO curve parameters are estimated with 52 TMS pulses, with absolute relative estimation errors (AREs) of less than 7%. The membrane time constant is estimated with 0.67% ARE, and the pulse width value tends to the critical pulse width with 0.16% ARE with 52 TMS pulses. The results confirm that the pulse width and amplitude can be tuned optimally and automatically to estimate the membrane time constant and IO curve parameters in real-time with closed-loop EMG-guided cTMS.

A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. Concurrency of pipeline circuits is defined as a function of the clock schedule and degree of wave pipelining. The authors then identify a special class of clock schedules, coincident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. It is shown that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking is derived. The authors compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization. >

This paper addresses verifying the timing of circuits containing level-sensitive latches in the presence of crosstalk We show that three consecutive periodic occurrences of the aggressor's input switching window must be compared with the victim's input switching window. We propose a new phase shift operator to allow aligning the aggressor's three relevant switching windows with the victim's input signals. We solve the problem iteratively in polynomial time, and show an upper bound on the number of iterations equal to the number of capacitors in the circuit. Our experiments demonstrate that eliminating false coupling results in finding a smaller clock period at which a circuit will run.

An algorithm has been developed for the automatic determination of the optimal clock waveforms for synchronous circuits containing level-sensitive latches. From a specification of only the number of clock phases, the rise and fall times of the clock phase transitions, and the order in which they occur, the algorithm computes the minimum time interval between the transitions, while accounting for the clock skew. Timing errors, such as incorrect hold times, are also detected. Existing procedures, in contrast, either verify if a circuit meets a given specification of these clock intervals, or they work with a very restricted set of clocking schemes. The procedure is iterative, and can be formulated as a linear programming problem. It yields an upper bound on the shortest valid clock period at each iteration. Results are presented for a simplified form of this algorithm, implemented in the transistor-level timing analysis program TAMIA.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Laser drilling is increasingly becoming a suitable choice for performing micro-drilling on advanced engineering and bio-compatible materials. In laser drilling operation, two types of major defects like spatter deposition and taper are generally encountered. In order to reduce the drilling defects, understanding the influence of process parameters on quality of hole is highly desirable. The influence of process parameters such as laser energy, pulse repetition rate, pulse width and gas pressure on the quality characteristics viz. circularity at entry and exit, taper and spatter area is studied in this work using Taguchi’s L27 orthogonal array. Analysis of variance (ANOVA) indicates that pulse width is most influencing parameter having percentage contribution of 43.981, 51.93, 88.28 and 39.94 for circularity at entry, circularity at exit, taper and spatter area respectively. It is observed that spatter area and heat affected zone (HAZ) increases with increase in laser energy and pulse width. This is due to the fact that heat input increases causing more material to melt but sufficient time is not allowed to completely flush away the molten material. As a result, heat is not dissipated adequately resulting in spatter formation and heat affected zone. The analysis also reveals that increase in pulse repetition rate and gas pressure leads to decrease in spatter area. Increase in pulse repetition rate causes increase in laser power leading to formation of laser supported absorption (LSA) wave which may cause the blockage of input energy. Hence, material ejection becomes less and scope for formation of spatter turns out to be less. Micrographs of drilled surface are analyzed using scanning electron microscope (SEM). The micrograph study suggests that increase in laser energy leads to increase in HAZ and circularity. The study also reveals that increase in pulse repetition rate leads to increase in burr formation in the hole periphery. Empirical models have been proposed to predict the quality characteristics of drilled hole. Mean relative error within 10% between the predicted value from empirical relations and experimental value for quality characteristics of hole indicates the validity of the proposed models. In order to obtain optimum parametric setting for all the quality characteristics, a well-known evolutionary approach known as genetic algorithm (GA) is used. The suggested best parametric conditions are definitely useful for the practitioners to avoid trial-and-error process of setting the process parameters for obtaining laser drilled holes of desired quality.

Operating frequencies of combinational logic circuits can be increased using Wave-Pipelining (WP), by adjusting the clock periods and clock skews. In this article, Built-In Self-Test (BIST) and System-on-Chip (SOC) approaches are proposed for automating this adjustment and they are evaluated by implementation of filters using a Distributed Arithmetic Algorithm (DAA) and sinewave generator using the COordinate Rotation DIgital Computer (CORDIC). Both the circuits are studied by adopting three schemes: wave-pipelining, pipelining, and nonpipelining. Xilinx Spartan II and Altera Cyclone II FPGAs with Nios II soft-core processor are used for implementation of the circuits with the BIST and SOC approaches, respectively. The proposed schemes increase the speed of the WP circuits by a factor of 1.19--2.6 compared to nonpipelined circuits. The pipelined circuits achieve higher speed than the WP circuits by a factor of 1.13--3.27 at the cost of increase in area and power. When both pipelined and WP circuits are operated at the same frequency, the former dissipates more power for circuits with higher word sizes and for moderate logic depths. The observation regarding the dependence of the superiority of the WP circuits with regard to power dissipation on the logic depth is one of the major contributions of this article.

One of the major requirements for testing VLSI devices is the validation of its timing specifications. Timing specifications would typically include frequency, propagation delays, minimum pulse width, phase offsets, setup time and hold time measurements. Although parametric specifications may exist for a nominal speed (frequency) of operation of the digital device, it may be necessary to characterize the device under test (DUT) to determine the highest operating frequency of the DUT and the required environmental parameters to run at the highest frequency. Characterization involves measurement of setup time, hold time and pulse width of the signals. In this paper, we have presented an automated AC (timing) characterization flow for digital circuit testing. We have recommended a STIL (Standard Tester Interface Language) like syntax for the timing tests. Various timing data (setup and hold time, propagation delay etc.) are measured in the first pass of the characterization process and are automatically back annotated to the timing test flow to reduce the total test cycle time. The approach will also help in finding the maximum operating frequency of the DUT and speed binning (i.e., sorting the devices based on their operating frequency).

A recent innovation in computational learning theory is the statistical query (SQ) model. The advantage of specifying learning algorithms in this model is that SQ algorithms can be simulated in the probably approximately correct (PAC) model, both in the absenceandin the presence of noise. However, simulations of SQ algorithms in the PAC model have non-optimal time and sample complexities. In this paper, we introduce a new method for specifying statistical query algorithms based on a type ofrelative errorand provide simulations in the noise-free and noise-tolerant PAC models which yield more efficient algorithms. Requests for estimates of statistics in this new model take the following form: “Return an estimate of the statistic within a 1±?factor, or return ?, promising that the statistic is less than?.” In addition to showing that this is a very natural language for specifying learning algorithms, we also show that this new specification is polynomially equivalent to standard SQ, and thus, known learnability and hardness results for statistical query learning are preserved. We then give highly efficient PAC simulations of relative error SQ algorithms. We show that the learning algorithms obtained by simulating efficient relative error SQ algorithms both in the absence of noise and in the presence of malicious noise have roughly optimal sample complexity. We also show that the simulation of efficient relative error SQ algorithms in the presence of classification noise yields learning algorithms at least as efficient as those obtained through standard methods, and in some cases improved, roughly optimal results are achieved. The sample complexities for all of these simulations are based on thed?metric, which is a type of relative error metric useful for quantities which are small or even zero. We show that uniform convergence with respect to thed?metric yields “uniform convergence” with respect to (?, ?) accuracy. Finally, while we show that manyspecificlearning algorithms can be written as highly efficient relative error SQ algorithms, we also show, in fact, thatallSQ algorithms can be written efficiently by proving general upper bounds on the complexity of (?, ?) queries as a function of the accuracy parameter?. As a consequence of this result, we give general upper bounds on the complexity of learning algorithms achieved through the use of relative error SQ algorithms and the simulations described above.

Before signals of a digital circuit reach steady state, gates can have multiple transitions. Since the power is dissipated in a CMOS circuit mainly due to transitions, the extra transitions increase power consumption. These transitions are the hazard pulses generated by a logic gate when signals arrive by paths of varying delays. The maximum width of a hazard pulse produced by a gate is the maximum difference between the delays of incident paths, which is generally much smaller than the clock period. We propose suppression of hazard pulses by increasing the delays of gates where hazards could have been generated. Thus, a hazard filtering gate has a delay which is at least as much as the differential delay of its input paths. We give examples to illustrate the novel technique and also indicate that the overall reduction in the circuit speed may not be too much with proper sizing of transistors, while there can be a significant reduction in power consumption.