Vertically Integrated CMOS Ternary Logic Device with Low Static Power Consumption and High Packing Density.

In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. 
 Keywords: Ternary logic, Ternary logic gates, VHDL language.

Tremendous amounts of data are being generated and should be processed during the massive employment of artificial intelligence and edge/cloud computing, necessitating computers with higher capabilities. However, as Moore's Law approaches its limit, enhancing computing capability through transistor miniaturization is becoming less feasible. New strategies for “more-than-Moore” are highly preferred to drive future technological advancements. Multiple-valued logic, especially ternary logic with its superior data density compared to traditional binary logic, offers a viable route to augment computing capability while reducing chip interconnections and dynamic power consumption. Despite the growing interest in ternary logic within academia and industry, its practical application remains limited due to the increased transistor count and connections required by earlier logic gate implementations. In this thesis, we present efficient implementation methods of basic ternary logic gates based on emerging nano-electronics including two-dimensional material-based transistors. The fabricated ternary devices show high performance in DC gain and low power consumption. Additionally, compact models of the devices have been established and calibrated, facilitating the circuit design and simulation in Electronic Design Automation (EDA) tools. At the circuit level, this thesis introduces novel ternary arithmetic circuits, including adders and multipliers, that are optimized for low power consumption and minimal delay. Finally, we showcase the practical benefits of ternary logic systems in data processing through the implementation of carry-free arithmetic circuits, underscoring their potential as a transformative computing paradigm.

As the development of binary systems forecasted to reach to its end, ternary system is gaining more attention. However, most ternary logic circuits were not considered to be a ‘true’ competitor to binary systems. To counter this common belief on ternary logic, in this study, we propose a ternary logic system based on depletion-mode MOSFETs and conventional MOSFETs that can truly compete with binary systems in terms of power and delay. Based on our novel circuitry of 11 logic gates, we illustrate that (1) our circuits consume near-zero static current on all logic states (−1, 0, +1), (2) our standard ternary inverter (STI) shows improved PDP of 71× and 245× compared to conventional CNTFET or memristor and MOSFET based ternary circuits, and (3) our balanced ternary full adder (BTFA) shows 48× improved power consumption compared to other ternary-device based adders and 5.3× improved power compared to the same devices. With our results, we highlight that ternary logic is now competitive to binary.

The article proposes a method for synthesizing ternary binary logic functions using a multi-threshold element, which significantly extends the capabilities of ternary logic compared to traditional binary logic. The aim of the work is to develop an algorithm for synthesizing ternary logic functions, based on the use of a multi-threshold element, which simplifies the design of logical circuits and reduces energy consumption while maintaining high data processing speed. The study includes a comparative analysis of ternary and binary logic functions, allowing an assessment of the advantages of ternary logic, particularly its ability to process more values than binary logic, which opens up new possibilities for creating more efficient computing devices. Specifically, ternary logic can reduce the complexity of circuits and hardware resource usage, while also enhancing performance in tasks where energy efficiency is critical. An essential part of the research is the development of an algorithm for synthesizing ternary binary logic functions based on a four-threshold multi-valued element. Furthermore, a software module was implemented to automate the synthesis of ternary functions. The program not only generates a graphical representation of the logical circuit but also formulates the analytical expression corresponding to the given logical function. This significantly simplifies the design and analysis of logical systems and enhances the efficiency of computations. Considering the high potential of ternary logic, the results of this work are significant not only for theoretical research but also for practical applications in the development of new computing devices and technologies. The further development of these ideas could contribute to the progress in computational systems working on new principles and open up new possibilities for optimizing technological processes in various fields of science and engineering.

Flexible memory devices have continued to attract more attention due to the increasing requirement for miniaturization, flexibility, and portability for further electronic applications. However, all reported flexible memory devices have binary memory characteristics, which cannot meet the demand of ever-growing information explosion. Organic resistive switching random access memory (RRAM) has plenty of advantages such as simple structure, facile processing, low power consumption, high packaging density, as well as the ability to store multiple states per bit (multilevel). In this study, we report a small molecule-based flexible ternary memory device for the first time. The flexible device maintains its ternary memory behavior under different bending conditions and within 500 bending cycles. The length of the alkyl chains in the molecular backbone play a significant role in molecular stacking, thus guaranteeing satisfactory memory and mechanical properties.

For a very long time truth-value gaps were under a cloud of suspicion because they were considered logically unmanageable. So Frege declared that:“as regards concepts we have a requirement of sharp delimitation; if this were not satisfied it would be impossible to set forth logical laws about them”.Three-valued logic promised to dispel the cloud but in the eyes of many it had promised more than it could deliver. So in response to Reichenbach's plea for a three-valued quantum logic Russell replied:“This is one of a number of questions as to which I am prevented from accepting a certain view by difficulties in carrying it out, but am prepared to alter my opinion if technical skill supplies an answer to my difficulties”.‘By now technical skill has supplied many alternative systems of three-valued logic, but few answers and numerous additional difficulties.’

Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) provide the capability to integrate display driver circuitry directly on display substrates, offering improved reliability and lower cost. However, long-term stability under DC bias stress is a critical issue for TFTs. Previous studies have shown that hydrogen, introduced into the channel film during the device fabrication process to passivate defects and thereby improving device performance, is the cause of the performance instability (Wu et al., 1990). Recent publications on deuterium post-metal annealing have demonstrated that deuterium passivated single crystalline MOSFETs exhibit superior reliability to MOSFETs passivated with hydrogen (Kizilyalli et al., 1997). Results indicated that, prior to hot carrier stress, deuterium and hydrogen anneals give identical improvement in device performance. In this study, we compare the performance and reliability of conventional top-gate, self-aligned polysilicon (poly-Si) thin-film transistors (TFTs) after passivation by plasma hydrogenation and plasma deuteration. We show that deuterium passivated poly-Si TFTs exhibit generally poorer pre-stress device characteristics than hydrogen passivated TFTs. In addition, reliability testing indicates that deuterium passivation does not provide greater resistance to performance degradation than hydrogen passivation for poly-Si TFTs.

Designing of an all-optical scheme for single input ternary logical operations

The low ionization rate of Mg acceptors in the p-gallium nitride (GaN) layer is a critical factor accounting for the low current density of E-mode GaN p-FETs. In this work, polarization-enhanced technology was adopted to enhance the ionization rate of the p-GaN channel. High-performance recessed-gate E-mode GaN p-FETs were fabricated to enable GaN complementary logic (CL) circuits. During fabrication, the channel thickness (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>) is found to be a critical parameter that influences the device metrics. With a decrease in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> (i.e., larger recess depth), a more negative threshold voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub>) is achieved; however, the trade-off is an increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{R}_{\biosc{on}}$</tex-math></inline-formula>. The E-mode GaN p-FET with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> = 32 nm exhibits a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> of -1.1 V, a high current density of 17.7 mA/mm, a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{I}_{\biosc{on}}$</tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{I}_{\biosc{off}}$</tex-math></inline-formula> of 6.9 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>7</roman></sup>, and a low subthreshold swing (SS) of 93 mV/dec. Furthermore, an E-mode n-channel p-GaN gate high electron mobility transistor (HEMT) was fabricated on the same epi-wafer, exhibiting a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> of 1.3 V and an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{R}_{\biosc{on}}$</tex-math></inline-formula> of 6 <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ω⋅</roman>mm. Finally, a GaN CL inverter was fabricated and demonstrated under <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>DD</roman></sub> = 6 V. Rail-to-rail voltage swing and low static power consumption were both achieved. This work further validates the feasibility of GaN CL integrated circuits and power integrated circuits (PICs).

The integration of multiple functional devices to achieve complex functions has become an essential requirement for future wearable biomedical electronic devices and systems. In this paper, we present a flexible multi-functional device composed of a biocompatible organic polymer resistive random-access memory (RRAM) and a photoresistor for wearable image sensing application. The resistive layer of organic polymer RRAM is composed by polychloro-para-xylylene (parylene-C), which is a flexible, transparent, biocompatibility and chemical stability polymer material. What is more, parylene-C is quite safe to be used within human body as it is a Food and Drug Administration (FDA)-approved material. This organic RRAM shows stable switching characteristics, low operation voltages (3.25 V for set voltage and $-$0.55 V for reset voltage), low static power consumption, high storage window and good retention properties ($>$10$^4$ s). A multi-functional device that can detect the light intensity of incident light and simultaneously store the information in the memory devices for wearable image sensing application was proposed and fabricated by integrating the organic resistive memory and a photoresistor. The threshold of incident light intensity can be easily adjust by changing the external voltage. This device is promising for building wearable electronic systems with various multiple functionalities.

The article presents a new approach to analyse leakage current and power dissipation in the low power devices like charge plasma based TFET (CP-TFET). Dual metal control gate (DMG) with high-K dielectric at source/channel interface has been proposed in DMG-CP-TFET to reduce leakage current and standby power. Control gate electrode split into two electrodes $\mathbf{CG}1 =4.5 \mathbf{eV}$ and $\mathbf{CG}2 =4 \mathbf{eV}$ , lower workfunction of control gate2 (CG2) forms a quantum well near the source/channel junction, which offers more resistance in the path of tunneled charge carries from source to channel region. Which results suppressed OFF-state current (leakage) and low static power consumption. Apart from these, quantum well phenomenon makes DMG-CP-TFET more robust for temperature rise. More over, the device reliability for length and workfunction variation of CG2 has been tested for DMG-CP-TFET.

Performance improvement of flexible piezoelectric energy harvester for irregular human motion with energy extraction enhancement circuit

This paper presents an energy-efficient 10-b pipelined ADC with a current-mode amplifier. The proposed amplifier achieves high gain, low static power consumption and supply voltage scalability without any calibration or timing control. The fabricated ADC in 65-nm CMOS process achieves FOMs of 14.3-to-36.9 fJ/c-s with a supply voltage range from 0.6-V to 1.0-V.

In the era of big data, the capability of computer systems must be enhanced to support 2.5 quintillion byte/day data delivery. Among the components of a computer system, main memory has a great impact on overall system performance. DRAM technology has been used over the past four decades to build main memories. However, the scalability of DRAM technology has faced serious challenges. To keep pace with the ever-increasing demand for larger main memory, some new alternative technologies have been introduced. Phase change memory (PCM) is considered as one of such technologies for substituting DRAM. PCM offers some noteworthy properties such as low static power consumption, nonvolatility, and capability of storing more than one bit per cell (multilevel cell, or MLC). However, the short lifetime and long access latency of PCM (specifically MLC PCM) require feasible and efficient solutions. In this article, based on the observation that applications access a significant number of read-friendly data blocks, we propose Express Read to prevent the MLC PCM read circuit to spend unnecessary time sensing the cells of a memory block. A read-friendly data block (RFDB) is composed of only “11” and “00” bit pairs, and thus upon sensing the most significant bit of a cell, the read operation can be early terminated to reduce the MLC read time and power consumption. Moreover, we increase the number of RFDBs using two simple techniques to better exploit the benefits of Express Read. Results obtained from full-system simulation near 6% performance improvement and 21% energy gain, on average, over the baseline system.

This study optimizes 28 nm planar MOSFET technology to reduce device leakage current and enhance switching speed. The specific aims are to decrease subthreshold swing (S.S.) and mitigate drain-induced barrier lowering (DIBL) effect. Silvaco TCAD software is used for process (Athena) and device (Atlas) simulations. For the further development of MOSFET technology, we implemented our device (planar 28 nm n-MOSFET) with high-k metal-gate (HK/MG), lightly doped drain (LDD), multi-spacers, and silicide. Simulation validation shows improvements over other 28 nm devices, with lower static power consumption and notable optimizations in both S.S. (69.8 mV/dec) and DIBL effect (30.5 mV/V).