Charge Pump Phase-locked Loop Research Articles (Page 1)

A low power low phase noise wide frequency range PLL

Abstract This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

The analysis of the behavior of Charge Pump Phase-Locked Loop (CP-PLL) is a challenging task due to its mixed-signal architecture. Out of its two types, i.e. Current Switched CP-PLL (CSCP-PLL) and Voltage Switched CP-PLL (VSCP-PLL), the prior produces symmetrical pump currents, resulting in an appropriate transient performance to be analyzed. The loop parameters are important to set the gain, target frequency, and assure the stability of the system. The more important is the bandwidth of the loop, which is dependent on the loop filter parameters to perform stable operation and locking time. In this paper, the impact of loop parameter variations on the overall transient behavior of the system is investigated. It has been shown that loop parameters play an important role to ease the design of mixed-signal PLLs.

The charge-pump Phase-Locked Loop (CP-PLL) is a widely used subsystem in wireless communication and smart system applications to perform the function of frequency synthesizer. Since the CP-PLL is a mixed-signal system, it is more complex to analyze the system behavior, especially when a voltage switched charge-pump-PLL (VSCP-PLL) is used. A more robust approach is required for such a non-linear pulse width modulated system, where the overall gain of the loop is varying due to non-constant pump current. To analyze the sampled behavior of a VSCP-PLL, the Event Driven (ED) model based on discrete-time phase equations is one of the powerful and resource efficient tool. In this brief, an autonomous ED model (time-independent and linear to fixed point) is developed for a second order VSCP-PLL by modifying the ED approach. The developed Autonomous ED-model is validated using the ED simulations in the locked state.

A spread-spectrum clock generator is proposed based on an in-band phase modulation. In a charge-pump phase-locked loop configuration, the input phase modulation signal is applied to the proposed charge-based discrete-time loop filter. The phase difference between the input phase modulation signal and the output clock feedback phase is sampled and applied to the control voltage of an oscillator. The loop gain of the clock generator pushes the output clock phase to accurately trace the input phase modulation signal. This article achieves 3.2% spread-spectrum modulation range and 26.51-dB spread-spectrum attenuation at 352-MHz output frequency using a 2-MHz reference frequency. The in-band modulation improves a design sensitivity, and a 298-ppm modulation range error is measured with over 140% K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> perturbations. This spread-spectrum clock generator is implemented in a 0.18-μm CMOS, and achieves 951-fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> period jitter while consuming 9.98 mW from a 1.8-V power supply.

A full-rate parallel pseudo random bit sequence (PRBS)-9 is systematically designed in the IBM 130-nm six-level metalization SiGe BiCMOS process with 2.5/3.3-V dual power supplies for the application of testing high-speed interconnects. The PRBS length and the phase difference between channels are studied using the methods of autocorrelation and cross correlation, respectively. The parallel PRBS streams can be used as stimuli for a serializer, and the autocorrelation method can be applied as a PRBS checker. It can also be used as stimuli for a four-level pulse amplitude modulation-4 signaling format transmitter with the least correlation between the LSB and the MSB by choosing the appropriate channel combinations. Two prototype boards are designed to test the PRBS along with an on-chip type-II third-order charge-pump phase-locked loop. Signal integrity issues are investigated. Finally, the PRBS has been demonstrated at board level with nonreturn-to-zero format operating at more than 10 Gb/s.

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

This paper employs a time-variant model to determine the exact small-signal loop transmission of second-order charge-pump phased-locked loops. The model predicts that a loop bandwidth of close to half the input frequency can be achieved. The large-signal behavior is also analyzed and two modes of oscillation are identified. The results are confirmed by means of circuit simulations.

Purpose – The linear analysis presented for the charge pump phase locked loops (CPPLLs) becomes inaccurate or incorrect where cycle slipping occurs. In this paper, an analytical approach is proposed, which explains the conditions in which cycle slipping happens. Using the analytical results, one can simply design or redesign a CPPLL to prevent or decrease cycle slipping and hence decreasing the locking time. The paper aims to discuss these issues. Design/methodology/approach – To obtain cycle slipping conditions, CPPLL's signals in the time domain are tracked and cycle slipping condition is investigated. Based on the proposed analysis, by comparing a simple function of system's parameters with a threshold, cycle slipping is predicted. Findings – The cycle slipping conditions are expressed in terms of system's parameters and the size of the input frequency step. The method is also generalized for a fast CPPLL with an aid-lock BBFC circuit. The good accuracy of the analytical predictions is verified using simulations in Matlab/Simulink. Originality/value – A new analytical method for cycle slipping prediction in CPPLLs is presented. A closed form equation in terms of system's parameters and input frequency step has been presented, which can predict the cycle slipping possibility in the system without a need to perform the full time-consuming simulations. This analytical method that uses the LambertW function's properties proposes a threshold to predict cycle slipping in the system. This method not only can be used by designers to predict cycle slipping but can also be used to design the CPPLL in order to remove or decrease cycle slipping. The method is also generalized for fast locking charge pump PLLs and as a case study, cycle slipping prediction in the BBFC-CPPLL is performed.

A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70 pspp, respectively, with a multiplication factor of 1024.

This paper explores a new topology of charge-pump PLL intended for ΔΣ-fractional-N frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path analog loop filter, the impact of charge-pump noise on PLL phase noise is reduced to negligible levels with no penalty on power dissipation. Additionally, the proposed topology enables an efficient cancellation of the ΔΣ quantization error, a novel scheme for the calibration of the loop filter parameters and a low-sensitivity VCO, which is beneficial in lowering the reference-spur level. The 3.0-to-4.0-GHz fractional-N synthesizer integrated in a 65-nm CMOS technology consumes 5 mW from a 1.2-V voltage supply. The flat phase noise is -105 dBc/Hz over the 5.5-MHz PLL bandwidth with a 40-MHz crystal reference.

In this work, a monotonic increasing piecewise-linear (PWL) memristor-based proportional-integral (PI) controller is analyzed. A periodic rectangular pulse current source is used as the input signal, and the proportionality constant of the PWL memristor-based PI controller is varied according to the amount of charge that passes through the memristor. A circuit is proposed to achieve zero net-charge injection for the memristor so that the memristance of the PWL memristor can be varied in the subsequent period. The proposed PWL memristor-based PI controller can be used in the design of the loop filter for the charge-pump phase-locked loop for achieving a faster dynamical response from an unlocked state to a locked state compared to conventional fixed proportional constant PI controllers.

This paper presents a loop-filter design method for third-order charge-pump phase-locked loops containing the loop delay. This method is derived from a z-domain phase-locked loop model. For a given loop bandwidth, we employ ripple swing control and adjust the filter pole to improve the spur performance. Another dynamic specification, the jitter peaking, is formulated as a H ∞ performance. The loop-filter design is transformed into an H ∞ optimization problem with the ripple swing constraint, which is solved using convex programming skills (linear matrix inequality, LMI). Compared to the conventional method, the method proposed in this study offers greater spur reduction without altering the loop bandwidth.

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

A second-order passive lead-lag loop filter for analog phase-locked loop (PLLs) is modified in this paper for the third-order charge-pump PLLs (CPPLLs). The analysis shows that the CPPLL employing the modified loop filter results in smaller area, lower power consumption, or better noise performance than the CPPLL employing the conventional loop filter.

This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%.

The effect of inclusion of different types of nonlinear amplifier (NLA) in the structure of a conventional charge pump phase locked loop (CP-PLL) has been studied. Through numerical simulation it has been shown that a particular class of NLA (cubic type nonlinearity) improves the acquisition performance of the CP-PLL whereas another class of NLA (limiter type nonlinearity) improves the tracking performance of the said system. The enhancement of acquisition performance of the NLA based CP-PLL has been examined by a prototype hardware experiment.

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 /spl mu/m CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>