An output queueing analysis of multipath ATM switches

In this paper, we present the performance analysis of bufferless slotted optical packet switching using non uniform traffic pattern. The mathematical analysis has been done to evaluate the packet loss rate and also compared with the existing uniform traffic pattern. In addition to this, we have also studied the performance of the non uniform traffic pattern with the uniform traffic pattern of various packet sizes. Under non-uniform traffic pattern, packet loss rate is very much reduced compared to the uniform traffic pattern and more number of packets has been transmitted for the same period of time.

Performance of ATM switch fabric using cross-point buffers

In this paper, we present the performance analysis of the 32×32 crosspoint queued (CQ) switch. The CQ switch architecture has been recently brought back into focus since modern technology enables an easy implementation of large buffers in crosspoints. An advantage of this solution is the absence of credit based control communication between linecards and schedulers. In this paper, the performances of four algorithms (longest queue first, round robin, exhaustive round robin and frame based round robin matching), are analyzed and compared. The results obtained for the CQ switch are compared with the output queued switch. Throughput, average cell latency and instantaneous packet delay variance are evaluated under uniform and nonuniform traffic patterns. Also, original iterative method for CQ switch throughput calculation under the uniform traffic is presented. The results will show that the longest queue first algorithm has the highest throughput in many simulated cases, but the highest average cell latency and delay variance among observed algorithms. It will also be shown that the choice of the scheduling algorithm does not play a role in the switch performance if the buffers are long enough. This will prove that some form of round robin based algorithms become a better choice for implementation due to their simplicity, small hardware requirements and avoidance of the starvation problem, which is a major drawback of the longest queue first algorithm. The proposed iterative method for throughput calculation gives results very close to the results obtained by numerous simulations, especially for larger switch and long buffers.

Performance of a Generic Non-blocking Packet Switch

This paper presents a unified model for analyzing multistage interconnection networks with multi-queue buffered strategies. Buffering strategies include SAFC (statically allocated fully connected), SAMQ (statically allocated multi-queue), DAMQ (dynamically allocated multi-queue), and DAFC (dynamically allocated fully connected) schemes. We develop a unified model to evaluate the performance of all these buffer allocation schemes under both uniform and nonuniform traffic patterns. The analytical model is validated through extensive simulations. Using the unified model, we conducted performance comparisons on the four buffer allocation schemes. It is shown that the DAFC scheme has the best performance over all the four buffer allocation schemes under both uniform and nonuniform loads.

USM, PULAU PINANG, 14 Mac 2018 – Lima pensyarah Universiti Sains Malaysia (USM) telah
\nmemenangi pingat dalam pertandingan sempena Ekspo Inovasi Islam (i-INOVA) 2018 yang
\nberlangsung pada 10-11 Mac lalu di Dewan Tuanku Canselor Universiti Sains Islam Malaysia (USIM),
\nBandar Baru Nilai, Negeri Sembilan.
\nIa merupakan kemenangan 100% kepada USM kerana kelima-lima produk/teknologi yang
\ndipertandingkan telah memenangi anugerah dan pingat.

Most Network-on-Chip routers dedicate a set of buffers to the input and/or output ports. This design decision leads to buffer underuti-lization especially when running applications with non-uniform traffic patterns. In order to maximize resource usage for performance and energy gains, we present a synchronous and elastic buffer implementation of a router architecture called Roundabout with intrinsic resource sharing. Roundabout is inspired by real-life traffic roundabouts and consists of lanes shared by multiple input and output ports. Roundabout offers performance improvement of 61% for uniform traffic pattern and up to 88% for non-uniform traffic pattern over the Hermes router, a typical input buffered router. In terms of power, it consumes 24% less than the Hermes router. Roundabout provides a highly parametric architecture that can produce different router configurations with varying topological trade-offs for performance gains without sacrificing area.

ATM is based on the efforts of the ITU-T Broadband Integrated Services Digital Network (B-ISDN) standard. It was originally conceived as a high-speed transfer technology for voice, video, and data over public networks. The ATM Forum has broadened the ITU-T's vision of ATM for extended use over public and private networks, multi-protocol support and mobile ATM. There are also some ATM applications in High Performance Computing (HPC). ATM is a packet switching technique based on a virtual circuit mechanism. Data flows are statistically multiplexed and communication resources are dynamically shared. Therefore the high performance ATM switch is essential for quality of services (QoS). This thesis introduces typical ATM switch architecture design and analyses design problems. The research objective is to propose a switch architecture design that can solve or improve those existing problems to achieve a superior performance. The research goal is an integrated ATM switch architecture that will handle both unicast and multicast packets. Unlike the usual design for the multicast ATM switch which concentrates on a cell copy network with a unicast switching network, the proposed switch architecture processes the network packets in a single switching block, and allows unicast and multicast packets to co-exist without competing. The switch design has a simple topology and operation principle and is easy to implement. Furthermore, no copy network is required. Three major components are proposed to form the core of the new switch architecture: the parallel buffering strategy for improved buffer performance, the fast table lookup algorithm for packet duplication and routing, and the relay ring controller for solving the contention problem associated with multiple packets destined for the same output port. A mathematical model is presented and its numerical results are analysed. In addition, the simulation algorithms for the proposed switching design are presented and compared against the switching design with input and output buffering strategies. The simulation results are also compared and analysed against the numerical results. A multicast traffic model is also presented. Its performance calculation for the proposed switch is achieved through simulation. Performance analysis is compared against the output buffering switch under the same multicast traffic model. The performance analysis shows that the proposed switch architecture achieves high throughput with low cell loss rate and low time delay. Its performance can be as good as the output buffering strategy or better. Therefore the proposed switch design has solved the problems associated with input and output buffering. This thesis also analyses the complexity of the proposed switch architecture and suggests a topology to build a large scale ATM switch. The suitability and feasibility for production implementation are also addressed.

Because of their ability of nonblocking and fault tolerance, multistage-multipath networks provide useful characteristics for ATM switches and large-scale parallel computers. In this paper an analytical model for the analysis of ATM switches based on multistage-multipath packet switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed model is general in that it analyzes ATM switches under uniform and nonuniform traffic. First, a general model of synchronous buffered switching element, using output buffering, under an assumption of finite buffer size for a very general class of traffic patterns, is presented. It is assumed that the subsequent stages of the network are nearly independent, and a model is extended for the entire network under this assumption. The analytical results obtained with the proposed model are then compared with the results obtained for single path networks, and it is shown that the model is general enough for the class of multipath networks.

Performance analysis of synchronous multibuffered packet-switching networks

A novel high-performance packet-switching architecture, called the knockout switch, has been recently proposed. It is a nonblocking, cost-effective switch suitable for broadband packet switching. The authors give equations which can be used to derive the packet loss probability and investigate the knockout switch under various uniform traffic patterns. They also compare the knockout switch with the multistage switch under various nonuniform traffic patterns. >

Pipelined circuit switching: Analysis for the torus with non-uniform traffic

The authors describe a simple adaptive routing scheme for datagram (connectionless) and virtual circuit (connection-oriented) transmission that relieves congestion resulting from nonuniform traffic patterns and network failures. The authors describe a fixed-routing algorithm for dedicated channel ShuffleNets. Based on the fixed routing algorithm, an adaptive routing scheme for datagram transmission is presented followed by performance results for uniform and nonuniform traffic patterns and fault tolerance. The adaptive routing of datagrams uses only the local queue size information available at the network interface units (NIUs) and redistributes the load as congestion develops. Since datagrams are individually routed through the network, they may not arrive at their destination in the order they were generated and may need to be resequenced. The authors compute an upper estimate on the resequencing buffer size for stream traffic. A virtual circuit version of the adaptive routing algorithm eliminates the need for resequencing buffers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A possible network architecture for a microcellular mobile telecommunication system based on packet transmission and ATM (Asynchronous Transfer Mode) switching is proposed. A full integration and internetworking with Broadband Integrated Services Digital Network are assumed. The performance of a generic nonblocking ATM switch under input traffic patterns that consider the effect of handovers is evaluated. Special attention is paid to the preservation of packet sequence integrity on a virtual channel. The generic ATM switch architecture has been analyzed under simplified network architecture assumptions by means of computer simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper proposes a scheme for pump-wavelength selection in an optical packet switch (OPS) with parametric wavelength converters (PWCs). In this scheme, pump wavelengths can be dynamically changed in all time slots, and more than one PWC is allowed to convert a wavelength in a chained manner. The objective of this scheme is to minimize the packet loss rates of the OPS. This scheme is called dynamic pump-wavelength selection with chained parametric wavelength conversion (DPS-C). DPS-C selects the pump wavelength for each PWC so as to maximize the number of successful requests, which refer to packets that wish to be forwarded to their requested output fibers. A PWC, which has the advantage of multiple wavelength conversion, uses a pump wavelength that can be flexibly chosen to define which wavelengths can be converted from/to. The set of original and converted wavelengths, where the pump wavelength is set in the middle of the two wavelengths, is called the conversion pair. Each PWC supports several conversion pairs. The OPS allows each wavelength to be converted using combinations of available conversion pairs, which are not used by any requests, from more than one PWC. A simulation shows that DPS-C outperforms the conventional scheme in terms of packet loss rates in both uniform and nonuniform traffic patterns.