Chapter 5 Processor Types And Instruction Sets

The simulation of parallel computers is discussed. In particular, a technique, called cross-profiling, that can be used to improve the efficiency of these simulations substantially is presented and evaluated. Cross-profiling, along with another simulation technique called execution-driven simulation, can be used to simulate one processor's instruction set (the target processor) with another processor that has a different instruction set (the host processor). Moreover, this technique is significantly faster than the usual method where several host instructions are executed to emulate the effect of executing a single instruction of the target processor. The cross-profiling technique is introduced, and it is shown how it can be combined with execution-driven simulation. The results of several experiments that demonstrate that the error introduced by cross-profiling is typically less than 1% are presented. >

Checking a page's accessibility (not mapped, read only or read/write) is sometimes useful for operating system kernels. We describe a technique for extending a processor's instruction set (by software) so that accessibility tests can in most cases be done faster than parsing the page table tree by software.

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set.

Aiming at construction of First-class curriculum, the courses "Microcomputer Principle and Interface Technology" and "Single-chip Microcomputer" are combined into one course according to there are similar instruction architecture. Two main section include into this combined course, microcomputer principle and interface technology. In the part of microcomputer principle focuses on the intel 80X86 processor architecture and instruction set. In the part of interface technology focuses on intel 8051 interface circuit and C language programming. The related experimental topics are also increased to provide more practical opportunities for students. The start time of this combined course is moved up to spring semester in second year. With these reforms above made this course to provide beneficial support for innovative practice of students. After more than three years of practice, the ability for students to use microcomputers and practical innovation have been greatly improved, which is reflected in the fact that students have achieved very good results in various innovation competitions.

It's like building a bridge. Once the main lines of the structure are right, then the details miraculously fit. The problem is the overall design. Freeman Dyson in Freeman Dyson: Mathematician, Physicist, and Writer, Interview with Donald J. Albers, The College Mathematics Journal, 25, No. 1, January 1994 . Now that we have been introduced to the fundamentals of Verilog, we make a slight change in course to return to the top level of the design flow shown previously in Figure 1.2. In particular, we now discuss the process by which we define the instruction set of a new processor. The instruction set architecture (ISA) of a processor defines all of the instructions available in the processor plus the storage elements that are accessible to the assembly language programmer. The contents of these storage elements, plus a few more that may not be directly accessible to the programmer, comprise the processor's state . In this chapter, we show how the ISA of a complete processor, which we call the Very Small Processor Architecture , or VeSPA for short, is defined, refined, and ultimately specified. This processor is quite simple, with only slightly more than a dozen instructions. However, it is a complete processor capable of executing programs written in a high-level language compiled with an appropriate compiler. We use this processor throughout the remainder of this text as a vehicle for demonstrating the entire processor design process when using the Verilog hardware description language. Instruction set design The design of an instruction set for a new processor is more of an art than a science.

Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are manifested as bit flips. In this work, we present a generalized methodology for monitoring code integrity at run-time in application-specific instruction set processors (ASIPs), where both the instruction set architecture (ISA) and the underlying micro architecture can be customized for a particular application domain. We embed monitoring microoperations in machine instructions, thus the processor is augmented with a hardware monitor automatically. The monitor observes the processor's execution trace of basic blocks at run-time, checks whether the execution trace aligns with the expected program behavior, and signals any mismatches. Since microoperations are at a lower software architecture level than processor instructions, the microarchitectural support for program code integrity monitoring is transparent to upper software levels and no recompilation or modification is needed for the program. Experimental results show that our microarchitectural support can detect program code integrity compromises with small area overhead and little performance degradation

A method for the identification of stuck-at bits on a data bus is described. Faulty data words are compared to isolate the stuck-at bits. A similar method can be used to identify an instruction which does not execute correctly in a processor instruction set. Here, faulty programmes, or faulty programme segments, are compared to isolate the faulty instruction. For both bus and instruction fault cases, probabilistic analyses are given with explicit formulas and data for the mean number of faulty samples required for diagnosis, and also the associated standard deviation. Both of these procedures use on-line data and are suitable for the diagnosis of intermittent faults.

The von Neumann processor has been the foundation of computing from the start. Today’s instruction processors are powerful and scale to thousands to yield large compute power, but a small fraction of the peak. The ASIC chip technology that implementations the fixed design microprocessor is placing significant constraints on the design of processors. At the same time reconfigurable Processors based upon FPGA chip technology are growing in capability and performance using a nontraditional processor architecture without instructions (the non-von Neumann architecture). Both processor types are trending to a common design point. This paper explores these trends and explains the technology of the emerging non-von Neumann processor and presents an example implementation.KeywordsField Programmable Gate ArrayClock RateCell ProcessorStream ProcessorProcessor TypeThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Automatic Software-Based Self Test Generation for Embedded Processors

Several techniques have been proposed to reduce the energy consumption of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with minimal change in the instruction set (IS), they often fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this chapter we present an energy-efficient IS synthesis that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction fetch count. Experimental results with a typical embedded RISC processor show that the proposed energy-efficient IS synthesis technique can generate application-specific ISs that are up to 40% more energy-efficient over the native IS for several application benchmarks.

Application-specific instruction-set processors (ASIPs) allow the designer to extend the instruction set of the base processor with selected custom instructions to tailor-fit the application. In this paper, with the help of a motivational example, we first demonstrate that different custom instructions are vulnerable to faults with varying probabilities. This shows that by ignoring the vulnerability to faults, traditional methods of instruction set customization can provide no guarantees on the reliability of the system. Apart from such inherent disparity in error vulnerability across custom instructions, each custom instruction can have multiple implementation choices corresponding to varying hardened levels. Hardening reduces the vulnerability to errors but this comes at the overhead of area costs and reduced performance gain. In this paper, we propose a framework to select custom instructions and their respective hardening levels such that reliability is optimized while the performance gain is satisfied and area costs are met as well. Our framework is based on a novel analytical method to compute the overall system reliability based on the probability of failure of individual instructions. Wide range of experiments that were conducted illustrate how our tool navigates the design space to reveal interesting tradeoffs.

This article discusses a MATLAB-to-C vectorizing compiler that exploits custom instructions, for example, for Single Instruction Multiple Data (SIMD) processing and instructions for complex arithmetic present in Application-Specific Instruction Set Processors (ASIPs). Custom instructions are represented via specialized intrinsic functions in the generated code, and the generated code can be used as input to any C/C++ compiler supporting the target processor. Furthermore, the specialized instruction set of the target processor is described in a parameterized way using a target processor-independent architecture description approach, thus allowing the support of any processor. The compiler has been used for the generation of application code for two different ASIPs for several benchmarks. The code generated by the compiler achieves a speedup between 2× --74× and 2× --97× compared to the code generated by the MathWorks MATLAB-to-C compiler. Experimental results also prove that the compiler efficiently exploits SIMD custom instructions achieving a 3.3 factor speedup compared to cases where no SIMD processing is used. Thus the compiler can be employed to reduce the development time/effort/cost and time to market through raising the abstraction of application design in an embedded systems/system-on-chip development context.

The advancing automation of the industrial production requires faster and more efficient programmable logic controllers. Today's controller architectures based on specialized processors to execute the STL application are at their limits. For any further improvement the architecture of these processors needs to evolve from single core in order execution to a multicore out of order architecture. This step can not occur without additions to the PLC's instruction set. Therefore a PLC processor instruction set simulation is required that allows a quick evaluation of the effectiveness and efficiency of instruction set changes as well as changes to the processor's architecture. Current architecture description languages (ADL) allow the fast modeling of these changes with enough flexibility for the planned improvements and provide fast simulation speed. This work presents for the first time an instruction set simulation environment for STL compatible PLC processors using the ADL ArchC as a base for further research.

Our investigation into architectural support for networking tasks began in late 1998, and it began with something of a coincidence. Fiuczynski was an active graduate student participant in the SPIN project at UW [2,3]. He had been writing a SPIN driver for a high-speed network interface card (NIC), and visited Crowley (at the time, a graduate student investigating the relationships between processor & memory architectures and desktop computer applications [4]) one afternoon to discuss the NIC's processor. Had either Fiuczynksi or Crowley been out of the office on that particular day, it is not clear that this collaboration would have emerged. As it happened, both were in the office that day and the NIC processor was very interesting: a dual-core MIPS-like processor built specifically for the NIC. In ensuing discussions, it became clear that-despite the simplicity of its instruction set and microarchitecture-the NIC processor was as a whole more interesting than the much larger and complex x86 processor of the host system. It was more interesting because, as a dual-core processor, it was different and in no way an incremental improvement upon the deeply pipelined CPUs that dominated computing at the time. (They still dominate PCs and servers, of course, but mobile, graphics and embedded chips represent a huge swath of relevant computing platforms today.) It represented evidence of a combination of commercial and technical justification for designing a new and different processor to handle networking tasks.