A short note on implementing “new” machine instructions by software for efficient test of page accessibility

Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are manifested as bit flips. In this work, we present a generalized methodology for monitoring code integrity at run-time in application-specific instruction set processors (ASIPs), where both the instruction set architecture (ISA) and the underlying micro architecture can be customized for a particular application domain. We embed monitoring microoperations in machine instructions, thus the processor is augmented with a hardware monitor automatically. The monitor observes the processor's execution trace of basic blocks at run-time, checks whether the execution trace aligns with the expected program behavior, and signals any mismatches. Since microoperations are at a lower software architecture level than processor instructions, the microarchitectural support for program code integrity monitoring is transparent to upper software levels and no recompilation or modification is needed for the program. Experimental results show that our microarchitectural support can detect program code integrity compromises with small area overhead and little performance degradation

The simulation of parallel computers is discussed. In particular, a technique, called cross-profiling, that can be used to improve the efficiency of these simulations substantially is presented and evaluated. Cross-profiling, along with another simulation technique called execution-driven simulation, can be used to simulate one processor's instruction set (the target processor) with another processor that has a different instruction set (the host processor). Moreover, this technique is significantly faster than the usual method where several host instructions are executed to emulate the effect of executing a single instruction of the target processor. The cross-profiling technique is introduced, and it is shown how it can be combined with execution-driven simulation. The results of several experiments that demonstrate that the error introduced by cross-profiling is typically less than 1% are presented. >

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set.

Chapter 5 Processor Types And Instruction Sets

Aiming at construction of First-class curriculum, the courses "Microcomputer Principle and Interface Technology" and "Single-chip Microcomputer" are combined into one course according to there are similar instruction architecture. Two main section include into this combined course, microcomputer principle and interface technology. In the part of microcomputer principle focuses on the intel 80X86 processor architecture and instruction set. In the part of interface technology focuses on intel 8051 interface circuit and C language programming. The related experimental topics are also increased to provide more practical opportunities for students. The start time of this combined course is moved up to spring semester in second year. With these reforms above made this course to provide beneficial support for innovative practice of students. After more than three years of practice, the ability for students to use microcomputers and practical innovation have been greatly improved, which is reflected in the fact that students have achieved very good results in various innovation competitions.

A method for the identification of stuck-at bits on a data bus is described. Faulty data words are compared to isolate the stuck-at bits. A similar method can be used to identify an instruction which does not execute correctly in a processor instruction set. Here, faulty programmes, or faulty programme segments, are compared to isolate the faulty instruction. For both bus and instruction fault cases, probabilistic analyses are given with explicit formulas and data for the mean number of faulty samples required for diagnosis, and also the associated standard deviation. Both of these procedures use on-line data and are suitable for the diagnosis of intermittent faults.

It's like building a bridge. Once the main lines of the structure are right, then the details miraculously fit. The problem is the overall design. Freeman Dyson in Freeman Dyson: Mathematician, Physicist, and Writer, Interview with Donald J. Albers, The College Mathematics Journal, 25, No. 1, January 1994 . Now that we have been introduced to the fundamentals of Verilog, we make a slight change in course to return to the top level of the design flow shown previously in Figure 1.2. In particular, we now discuss the process by which we define the instruction set of a new processor. The instruction set architecture (ISA) of a processor defines all of the instructions available in the processor plus the storage elements that are accessible to the assembly language programmer. The contents of these storage elements, plus a few more that may not be directly accessible to the programmer, comprise the processor's state . In this chapter, we show how the ISA of a complete processor, which we call the Very Small Processor Architecture , or VeSPA for short, is defined, refined, and ultimately specified. This processor is quite simple, with only slightly more than a dozen instructions. However, it is a complete processor capable of executing programs written in a high-level language compiled with an appropriate compiler. We use this processor throughout the remainder of this text as a vehicle for demonstrating the entire processor design process when using the Verilog hardware description language. Instruction set design The design of an instruction set for a new processor is more of an art than a science.

This tutorial offers a pedagogical guide to hybrid quantum processors that integrate discrete-variable (DV) qubits and continuous-variable (CV) oscillators. Aimed at computer scientists, engineers, and physicists, it provides an overview of the experimental, algorithmic, and architectural aspects of this novel and rapidly developing hardware model. Experimental realizations of this model include superconducting, trapped-ion, and neutral-atom platforms. By combining DV and CV components, hybrid oscillator-qubit processors enable a powerful new paradigm that offers complementary strengths for quantum control, error correction, computation, and simulation. Working toward the goal of a full-stack system connecting applications to CV-DV hardware, we define and formulate abstract machine models and instruction set architectures. These essential abstractions enable codesign of hardware and software, and resource estimation for exploring the potential of current and future hardware for computational and simulation tasks. Using these abstractions, we present both new and existing examples that illustrate the benefits of hybrid CV-DV processors relative to traditional DV-only hardware in computation as well as quantum simulation of physical models. Examples include algorithms for transferring states between DV and CV systems, performing the quantum Fourier transform, and simulation of lattice gauge theories. Relative to qubit-only hardware, the bosonic degrees of freedom natively available in hybrid architectures can substantially reduce the circuit complexity of simulations for physical models containing bosons. A key technique is the extension of quantum signal processing ideas to CV-DV systems. This work is intended to serve as a timely and comprehensive guide to this relatively unexplored yet promising approach to quantum computation and to provide a road map to guide future development.

Background: The development of technology, both hardware and software, is rapidly advancing due to the growth of Artificial Intelligence (AI), which simplifies many human activities, including the software testing process. This research journal discusses how software testing is conducted through a Quality Management System (QMS). Objective: The journal examines whether software testing processes are related to QMS, how significantly QMS supports software testing, and the differences between testing with QMS and without QMS. Methods: This study outlines the stages of software testing through QMS, such as Software Quality Assurance (SQA), Quality Control (QC), Test Maturity Model Integration (TMMI), and performance indicators. According to the American Society for Quality (ASQ), QMS is a formal and documented system consisting of policies, processes, and procedures designed to achieve an organization's quality policies and objectives. Results: Several experts also define QMS as a system that focuses on improving customer satisfaction, process consistency, efficiency, and the overall quality of products or services. Software, according to Roger S. Pressman, is a set of instructions (programs), data structures that allow information manipulation, and related documentation describing operations and functions. Conclusion: Overall, QMS not only improves software product quality but also strengthens the testing process, making it more optimal, efficient, and aligned with organizational goals. The integration of QMS frameworks such as ISO 9001:2015, CMMI, and TMMI provides organizations with a competitive advantage by ensuring consistent delivery of high-quality software products that meet or exceed customer expectations.

The authors propose a synthesis methodology for high-performance pipelined instruction set processors. Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of the Advanced Design Automation System (ADAS) which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is to perform pipeline scheduling with any fixed instruction-latency, and generate a reorder table for a back-end compiler to resolve potential pipeline hazards existing in the design. Models for performance and cost of both hardware and software are developed to characterize the design space. A synthesis example of a simple instruction set processor illustrates Piper's synthesis capabilities and how the performance and cost of hardware and software are estimated. >

Application-specific instruction-set processors (ASIPs) allow the designer to extend the instruction set of the base processor with selected custom instructions to tailor-fit the application. In this paper, with the help of a motivational example, we first demonstrate that different custom instructions are vulnerable to faults with varying probabilities. This shows that by ignoring the vulnerability to faults, traditional methods of instruction set customization can provide no guarantees on the reliability of the system. Apart from such inherent disparity in error vulnerability across custom instructions, each custom instruction can have multiple implementation choices corresponding to varying hardened levels. Hardening reduces the vulnerability to errors but this comes at the overhead of area costs and reduced performance gain. In this paper, we propose a framework to select custom instructions and their respective hardening levels such that reliability is optimized while the performance gain is satisfied and area costs are met as well. Our framework is based on a novel analytical method to compute the overall system reliability based on the probability of failure of individual instructions. Wide range of experiments that were conducted illustrate how our tool navigates the design space to reveal interesting tradeoffs.

This article discusses a MATLAB-to-C vectorizing compiler that exploits custom instructions, for example, for Single Instruction Multiple Data (SIMD) processing and instructions for complex arithmetic present in Application-Specific Instruction Set Processors (ASIPs). Custom instructions are represented via specialized intrinsic functions in the generated code, and the generated code can be used as input to any C/C++ compiler supporting the target processor. Furthermore, the specialized instruction set of the target processor is described in a parameterized way using a target processor-independent architecture description approach, thus allowing the support of any processor. The compiler has been used for the generation of application code for two different ASIPs for several benchmarks. The code generated by the compiler achieves a speedup between 2× --74× and 2× --97× compared to the code generated by the MathWorks MATLAB-to-C compiler. Experimental results also prove that the compiler efficiently exploits SIMD custom instructions achieving a 3.3 factor speedup compared to cases where no SIMD processing is used. Thus the compiler can be employed to reduce the development time/effort/cost and time to market through raising the abstraction of application design in an embedded systems/system-on-chip development context.

In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations.In contrast to previous system modeling approaches this approach tries to model the whole system and especially the memory hierarchy in a structural and semantically accessible way. Previous approaches primarily support generation of simulators or retargetable code selectors and thus concentrate on pure behavioral models or describe only the processor instruction set in a semantically accessible way, A simple, database-like, interface is offered to the optimization developer, which in conjunction with the MACCv2 framework enables rapid development of source-level architecture independent optimizations.

Embedded software development relies on various tools - compilers, simulators, execution time estimators - that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain: significant benefits could be expected if they were automatically generated from models expressed in a dedicated modeling language. In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture Description Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set), resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions). This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools follow the Model-Driven Engineering philosophy: metamodeling and model transformations have been successfully applied to the automatic generation of processor simulators.