Exploration on the First-class Courses Construction of Microcomputer Principles and Single Chip Microcomputer Interface Technology

Research and Practice of Course Design on Microcomputer Principle and Interface Technology

The course principle and interface technology is a professional basic courses of the Faculty of science and engineering, but for beginners, the knowledge point is range, abstract and difficult to understand. For beginners to more thoroughly understand the concepts of the course, this article listed some related instances of the application of analogy method in the course. It can make the abstract problems to visualize, enhance learners' learning interest, and improve their learning efficiency. Index Terms - analogy method, microcomputer principle and interface technology, teaching. I. Microcomputer principle and interface technology

The simulation of parallel computers is discussed. In particular, a technique, called cross-profiling, that can be used to improve the efficiency of these simulations substantially is presented and evaluated. Cross-profiling, along with another simulation technique called execution-driven simulation, can be used to simulate one processor's instruction set (the target processor) with another processor that has a different instruction set (the host processor). Moreover, this technique is significantly faster than the usual method where several host instructions are executed to emulate the effect of executing a single instruction of the target processor. The cross-profiling technique is introduced, and it is shown how it can be combined with execution-driven simulation. The results of several experiments that demonstrate that the error introduced by cross-profiling is typically less than 1% are presented. >

Checking a page's accessibility (not mapped, read only or read/write) is sometimes useful for operating system kernels. We describe a technique for extending a processor's instruction set (by software) so that accessibility tests can in most cases be done faster than parsing the page table tree by software.

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set.

It's like building a bridge. Once the main lines of the structure are right, then the details miraculously fit. The problem is the overall design. Freeman Dyson in Freeman Dyson: Mathematician, Physicist, and Writer, Interview with Donald J. Albers, The College Mathematics Journal, 25, No. 1, January 1994 . Now that we have been introduced to the fundamentals of Verilog, we make a slight change in course to return to the top level of the design flow shown previously in Figure 1.2. In particular, we now discuss the process by which we define the instruction set of a new processor. The instruction set architecture (ISA) of a processor defines all of the instructions available in the processor plus the storage elements that are accessible to the assembly language programmer. The contents of these storage elements, plus a few more that may not be directly accessible to the programmer, comprise the processor's state . In this chapter, we show how the ISA of a complete processor, which we call the Very Small Processor Architecture , or VeSPA for short, is defined, refined, and ultimately specified. This processor is quite simple, with only slightly more than a dozen instructions. However, it is a complete processor capable of executing programs written in a high-level language compiled with an appropriate compiler. We use this processor throughout the remainder of this text as a vehicle for demonstrating the entire processor design process when using the Verilog hardware description language. Instruction set design The design of an instruction set for a new processor is more of an art than a science.

Chapter 5 Processor Types And Instruction Sets

The characteristics and applications of the system for welding machines based on SCM , based on PLC control system and PC-based industrial control system was introduced. It has certain significance to the design of welding machine control system.

Data Acquisition and Interface Technology is a compulsory course for the major of measurement and control technology and instrument in Southwest Petroleum University, and it is a basic course combining theory and practice closely. The traditional experiment teaching is limited by various conditions. Students can only complete the specific experiment content with limited experiment equipment in limited time and place. It is an effective way to solve the above problems by introducing virtual simulation technology to construct the remote measure and control experiment platform to carry on the reform of the traditional experiment teaching mode. The remote measurement and control platform uses virtual technology to form the test function into a software module with image-realistic panel controls, to complete the test and processing tasks as if doing experiments in the laboratory, to move the experiment teaching into the classroom, to move into the network and life, and to realize the perfect fusion of theory and practice. It has been proved that the application of the remote measurement and control platform in the experimental teaching of the course of Data Acquisition and Interface Technology can improve the teaching effect. Moreover, the cost is low and the efficiency is high, so that students cannot be limited by time and space, improve their self-learning ability and practical innovation ability, which is of great significance in the teaching of the course of measurement and control technology.

Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are manifested as bit flips. In this work, we present a generalized methodology for monitoring code integrity at run-time in application-specific instruction set processors (ASIPs), where both the instruction set architecture (ISA) and the underlying micro architecture can be customized for a particular application domain. We embed monitoring microoperations in machine instructions, thus the processor is augmented with a hardware monitor automatically. The monitor observes the processor's execution trace of basic blocks at run-time, checks whether the execution trace aligns with the expected program behavior, and signals any mismatches. Since microoperations are at a lower software architecture level than processor instructions, the microarchitectural support for program code integrity monitoring is transparent to upper software levels and no recompilation or modification is needed for the program. Experimental results show that our microarchitectural support can detect program code integrity compromises with small area overhead and little performance degradation

A method for the identification of stuck-at bits on a data bus is described. Faulty data words are compared to isolate the stuck-at bits. A similar method can be used to identify an instruction which does not execute correctly in a processor instruction set. Here, faulty programmes, or faulty programme segments, are compared to isolate the faulty instruction. For both bus and instruction fault cases, probabilistic analyses are given with explicit formulas and data for the mean number of faulty samples required for diagnosis, and also the associated standard deviation. Both of these procedures use on-line data and are suitable for the diagnosis of intermittent faults.

Optoelectronic technology is a high-tech that combines traditional optical technology with modern electronic technology and computer technology. It is an important means to obtain optical information or extract other information (such as force, temperature, sound, current and biology) by means of light. In this paper, the detection circuit of preamplifier is designed with single chip microcomputer as the core, and the faults in real-time operation can be eliminated through the cooperation of software and hardware. The detection system can be used conveniently by connecting the widely used USB interface with preamplifier. According to the noise characteristics of photoelectric detection circuit, LMS adaptive filter is designed and simulated, and good results are obtained.

Several techniques have been proposed to reduce the energy consumption of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with minimal change in the instruction set (IS), they often fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this chapter we present an energy-efficient IS synthesis that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction fetch count. Experimental results with a typical embedded RISC processor show that the proposed energy-efficient IS synthesis technique can generate application-specific ISs that are up to 40% more energy-efficient over the native IS for several application benchmarks.

Internet plus education has hitherto unknown the opportunities and challenges of the development of modern occupation education. Based on the super star "one level and three ends" intelligent teaching system, modern information technology is deeply integrated into the reform and practice of mixed teaching mode of computer specialty in higher vocational colleges. Taking the teaching of C language programming as an example, reconstruct multiple curriculum objectives, reform the curriculum teaching content system, create MOOC courses with higher vocational characteristics, build a "MOOC + SPOC + flipped classroom" teaching mode, carry out "3 + 2" mixed teaching, and build a three-dimensional curriculum ideological and political system of "country, society and individual", Create a diversified assessment method combining process and summative assessment, organically integrating online and offline classes and three teaching stages before, during and after class. Teaching practice shows that this model is conducive to stimulate higher vocational students’ learning interest, cultivate higher vocational students’ autonomous learning ability, promote higher vocational students’ in-depth learning, improve higher vocational students’ learning ability, and achieve good teaching results.