Design and Implementation of a Reliable Reconfigurable Imaging System

We investigate the implementation of triple modular redundancy (TMR) with different number of voters in a softcore RISC-V microprocessor to mitigate radiation-induced faults in the configuration memory (CRAM) of SRAM-based FPGA. The case-study microprocessor is the Steel Core implemented in AMD Xilinx 7-Series/Zynq-7000 device, executing benchmark software on the FreeRTOS operating system. We implemented coarse-grained TMR (CGTMR) and fine-grained distributed TMR (FGDTMR) using an automated redundancy and voter insertion tool. TMR is used in combination with memory scrubber featured by the FPGA hardware, which uses error correction codes (ECC) to revert radiation-induced faults in CRAM. Fault injection in CRAM emulating radiation-induced faults is used to evaluate the benefits of both TMR and ECC. Under fault injection, combining the fault masking capability of TMR with the self-healing by ECC, improved mean time between failures (MTBF) up to 5×. ECC alone did not improve significantly the fault tolerance. Without ECC, FGDTMR improves MTBF in 2×, but at a higher cost in circuit area and resources usage. When combined with ECC, the CGTMR provides fault tolerance comparable to FGDTMR but with 30% less resources usage.

High reliable reconfigurable applications today require system platforms that can easily and quickly detect and correct single event upsets. This capability, however, can be costly for FPGAs. This paper demonstrates a technique for detecting and repairing SEUs within the configuration memory of a Xilinx Virtex-4 FPGA using the ICAP interface. The internal configuration access port (ICAP) provides a port internal to the FPGA for configuring the FPGA device. An application note demonstrates how this port can be used for both error injection and scrubbing (L. Jones, 2007). We have extended this work to create a fault tolerant ICAP scrubber by triplicating the internal ICAP circuit using TMR and block memory scrubbing. This paper will describe the costs, benefits, and reliability of this fault-tolerant ICAP controller.

Dynamic Partial Reconfiguration is an important feature of modern FPGAs as it allows for better exploitation of FPGA resources over time and space. The Internal Configuration Access Port (ICAP) enables DPR from within an FPGA chip, leading to the possibility of fully autonomous FPGA-based systems. This paper presents a novel high performance and fault-tolerant ICAP controller which can operate at a high speed and recover from emerging faults. Test results showed that our ICAP controller is 25 times faster than the Xilinx' XPS_HWICAP IP core. We demonstrate the use of Triple Modular Redundancy (TMR) in some of the ICAP controller components which have the ability to reconfigure the rest of the ICAP controller when faults are detected. This method is shown to have a 49% smaller area footprint compared to traditional full TMR.

The field-programmable gate arrays (FPGAs) are widely used in varies fields in recent years. However, because of large amounts of configuration memories in FPGAs are used to implement logic and routing, the single event upset (SEU) problem makes them not feasible for applications that need high reliability. Moreover, as the threshold voltage becomes lower with the development of silicon process technology, the configuration memories are becoming more sensitive to SEU. Therefore, FPGAs require new technology to improve its dependability. In this research, we first develop a new Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input COGRE with the novel error detect and correct circuit save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.

Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR–MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR–MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15–23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin.

Using Bayesian networks in reliability evaluation for subsea blowout preventer control system

Fault tolerance in electronic systems is essential in harsh environments such as space. However, FPGAs that can be used to accelerate various computations are prone to configuration memory faults that determine their function. Repairing these faults is essential to increase system resilience. For this purpose, the partial dynamic reconfiguration controller is necessary. We force the controller to be on the same FPGA with a payload circuit to design a comprehensive system inside one FPGA. We create and thoroughly test a new reconfiguration controller to increase the system's resiliency with the ability to repair itself during its own operation. For this purpose, the FPGA controller is in coarse-grained triple modular redundancy to be able to recover despite the failure of any of its modules. The proposed controller has been tested to increase the resilience of circuits from a set of benchmark circuits. The entire system with the controller was evaluated on an actual FPGA, where faults were injected directly into the configuration memory of this FPGA. Reliability parameters are measured by a platform designed for this purpose, partly directly on the tested FPGA. As we can see from the results, the mean time to failure has been increased by up to 69% compared to a system equipped with only triple modular redundancy with a reasonable amount of hardware resources. The competitive solution brings only a 42% improvement in resilience with similar parameters.

Triple modular redundancy (TMR) is one of the most common techniques in fault-tolerant systems, in which the output is determined by a majority voter. However, the design diversity of replicated modules and/or soft errors that are more likely to happen in the nanoscale era may affect the majority voting scheme. Besides, the significant overheads of the TMR scheme may limit its usage in energy consumption and area-constrained critical systems. However, for most inherently error-resilient applications such as image processing and vision deployed in critical systems (such as autonomous vehicles and robotics), achieving a given level of reliability has more priority than precise results. Therefore, these applications can benefit from the approximate computing paradigm to achieve higher energy efficiency and a lower area. This article proposes an energy-efficient approximate reliability (X-Rel) framework to overcome the aforementioned challenges of the TMR systems and get the full potential of approximate computing without sacrificing the desired reliability constraint and output quality. The X-Rel framework relies on relaxing the precision of the voter based on a systematical error bounding method that leverages user-defined quality and reliability constraints. Afterward, the size of the achieved voter is used to approximate the TMR modules such that the overall area and energy consumption are minimized. The effectiveness of employing the proposed X-Rel technique in a TMR structure, for different quality constraints as well as with various reliability bounds, is evaluated in a 15-nm FinFET technology. The results of the X-Rel voter show delay, area, and energy consumption reductions of up to 86%, 87%, and 98%, respectively, when compared to those of the state-of-the-art approximate TMR voters. Also, the effectiveness of the proposed X-Rel-based TMR structure is assessed in four benchmark applications from different domains. For these benchmarks, the results show <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.59\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.35\times $ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.39\times $ </tex-math></inline-formula> energy-delay-area-product (EDAP) reduction for less than 1%, 5%, and 10% output quality degradations, respectively. Finally, an image processing application is benchmarked to evaluate the X-Rel framework efficacy in the presence of errors, where the results show up to a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.78\times $ </tex-math></inline-formula> higher output image quality in comparison with the typical TMR voters.

Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable gate arrays (FPGAs) by masking the effects of upsets in the configuration memory. Although TMR is most effective when applied to an entire FPGA design, a reduction in the sensitive cross section of an FPGA design can be obtained by applying TMR selectively. This article explores several approaches for selecting components to triplicate. The benefit is a reduction in the neutron cross section for any output error as a percentage compared to that of a non-triplicated design. The cost is the percentage of components triplicated. The goal is to maximize the benefit-cost ratio. Twenty-five different selections are tested on a benchmark design. Some selections increase the cross section; others decrease the cross section significantly.

We introduce a re-configurable system design for positron emission tomography (PET) for purpose of maximizing the cost effectiveness of PET. In this new design concept, a PET system employs a small number of compact, flat-panel (cFP) PET detectors (which we believe will be made available in near future by us or others) to assume various scanner geometries so that the performance properties desired in various imaging applications can be met by a single PET system. For purpose of demonstration, we consider the design of a re-configurable small-animal system consisting of four cFP detectors that are approximately 8×8 cm2 in size and made of 10mm thick LSO. We consider four geometries for the scanner and conduct Monte-Carlo simulations to study their sensitivity, scatter fractions, random fractions, and noise-equivalent count rates. Our results indicate that, in terms of sensitivity and imaging field-of-view (FOV) the re-configurable system that we consider are very promising for small-animal imaging.

Partial Reconfiguration is a common technique on FPGA platforms to load hardware accelerators at runtime without interrupting the remaining system. One crucial element is the time needed for reconfiguration as it affects usability, performance and energy consumption. Furthermore, many systems have to share partial areas between multiple applications and users. In this paper, we introduce a novel open-source reconfiguration manager for Xilinx Zynq SoCs which a) allows partial area sharing and b) includes a hybrid reconfiguration approach utilizing both the Processor Configuration Access Port (PCAP) and the Internal Configuration Access Port (ICAP) in order to minimize reconfiguration time and system energy consumption. We evaluate our design and identify the sweet spots between energy consumption and latency of accelerator availability with an example use case. By means of the hybrid approach, a speedup for the full configuration after powering on the FPGA of up to 64 % in comparison to solely using the PCAP interface can be achieved.

Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement

Urban buildings use a large amount of electrical energy every day, especially for cooling. One common reason Fault tolerance is a critical requirement in safety-critical and high-reliability digital systems such as aerospace electronics, medical devices, industrial automation, and communication infrastructure. This project focuses on the design and development of a fault-tolerant digital system using the Triple Modular Redundancy (TMR) technique [1], [3]. In a TMR architecture, three identical modules execute the same operation in parallel, and a majority voting mechanism determines the correct output even if one module fails due to transient faults, permanent hardware failures, or radiation-induced errors [1]. The proposed system implements replication at the hardware level and incorporates a robust majority voter circuit to ensure continuous operation without performance degradation [2], [3]. The design is simulated and validated using digital design tools to analyze system behavior under fault-injection scenarios. Performance metrics such as reliability, error-masking capability, propagation delay, and resource utilization are examined to evaluate the effectiveness of the TMR approach. The results demonstrate that TMR significantly enhances system reliability and resilience by masking single-point failures, making it a practical solution for mission-critical applications where system downtime or incorrect outputs are unacceptable [1], [3]. This project provides a comprehensive understanding of fault-tolerant design strategies and highlights the trade-offs between hardware redundancy, system complexity, and operational reliability.

The hunt for increased reliability in systems for critical applications is a never-ending process and is a point of concern for designers in several different fields, such as nuclear reactors. This concern becomes more prominent when a new device technology is integrated into the options for the development of those systems, such as programmable logic devices like the FPGA. With the constant breakthroughs in this technology, there has been an increase in the capacity and the performance of FPGAs. Nevertheless, new methods to keep fault tolerance at an appropriate level for critical applications in hardware must be considered, particularly due to the transient nature of some radiation-induced faults. This work proposes a resilient and adaptable hardware architecture that increases the reliability of circuits implemented in FPGAs, based on a classic active redundancy model, Triple Modular Redundancy with spares. Also, it brings forth a novel hardware architecture that can easily be ported to different FPGA models without compromising performance, reliability, and availability. We discuss and analyze these requirements for the proposed architecture and show that it is more reliable and keeps this reliability for longer periods of time than redundant solutions that use more area.

Triple-modular redundancy (TMR) is a classical technique for improving the reliability of digital systems. However, applying TMR to microcomputer systems may not improve overall system reliability because voter circuits may contribute as much to system unreliability as the microprocessors themselves. We examine the issues that affect the effectiveness of TMR for transient recovery and the reliability of semiconductor memory systems. With careful application, TMR can improve the mission time of a small system by a factor of 3 or more.