Functionally Undetectable Interconnect Faults in Chiplet-Based Designs

A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to fix certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.

A challenging issue is the derivation of a finite test suite from a given LOTOS specification modeled by a labeled transition system (LTS) such that complete fault coverage is guaranteed for a certain class of implementations with respect to a particular conformance relation. It is shown in this paper that this problem can be solved by translating an LTS into an input/output finite state machine (FSM) for trace or failure semantics, respectively, and subsequently applying existing FSM-based methods for test derivation with complete fault coverage. It is also demonstrated that the obtained tests can be further optimized taking into account the specifics of the FSMs constructed from the LTSs.KeywordsTest SuiteFinite State MachineLabel Transition SystemConformance TestingImplementation Under TestThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

A 16 × 2 two-dimensional (2-D) array of single-photon avalanche diodes integrated in a complementary metal-oxide-semiconductor (CMOS) process is presented. Each pixel is made up of an avalanche photodiode biased in the so-called Geiger mode, a quenching resistor, and a basic comparator. To implement the photon counting verification on the chip, a build-in-self-test (BIST) module is added. Full integration allows for 10218.70 μm2 of total cell area and 1.7837 mW of power consumption, which is about 38% less than the 2.8567 mW of the prior design. The circuit is capable of running at a 200 MHz counting rate. The array's internal signals and status can be monitored while it is being tested or used thanks to the built-in logic block observation module demonstrated in this paper. The effectiveness and efficiency of testing can be increased, as well as the performance of the readout electronics, by adding Kogge-Stone adder and BIST circuits to the array design. The ability to quickly adapt the design to suit a particular application is another undeniable advantage of CMOS integration, which also paves the way for on-chip data processing.

A functional test sequence for a design may not be effective as a manufacturing test for a logic block in the design because it achieves a low gate-level fault coverage. This paper describes a procedure for selecting a clock sequence that increases the gate-level fault coverage of a functional test sequence when it is used for testing a subset of logic blocks. The procedure deactivates the clocks to the logic blocks in the subset when a primary input vector has a negative effect on their fault coverage. The procedure is different from earlier test generation and test compaction procedures in that it increases the fault coverage without modifying the functional test sequence. It thus preserves some of the functional characteristics and the test application process for the sequence. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure.

Most FPGAs use Look-Up Table (LUT) as the basic logic block. Input sharing look-up table (ISLUT) architecture is a cluster architecture, which can be configured as one 6-input LUT, two smaller LUTs or other modes. In this paper, several ISLUT architectures are added into Verilog-to-Routing (VTR) tool to compare with standard 6-input basic logic element (BLE6) architecture. Experimental results show that those input sharing architectures can achieve an 18.02% improvement for critical path delay and a 35.28% improvement for total used logic block area on average compared with standard BLE6. Among all those modes, the architecture that consists of one 5-input LUT, one 4-input LUT and two 3-input LUTs shows a better performance of 19.66% for the critical path delay and 37.68% for total used logic block area compared with standard BLE6. It also shows 14.28% improvement for the critical path delay and 10.00% for total used logic block area can be achieved compared with the ALM architecture.

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.

Functional test sequences were shown to detect unique defects in VLSI circuits. This is thought to be due to the fact that they are applied at-speed. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, scan-based stuck-at tests, as well as other types of tests, are typically also applied. This increases the amount of test resources required for test application. We describe a procedure for inserting (limited) scan operations into a functional sequence in order to improve its stuck-at fault coverage, thus reducing or eliminating the need for separate scan-based stuck-at tests. Between scan operations, the functional test sequence can still be applied at-speed; however, a higher stuck-at fault coverage is achieved.

Test cost is increasingly becoming a major component of a product's design cost in scaled technologies. Exponential increase in test data volumes for sub-45 designs, especially for testing delay faults has led to large increase in ATE cost and test application time. In order to reduce external test cost, Logic BIST has been explored as a possible alternative to manufacturing test [1-5]. However, this paper shows that a large number of faults in BIST logic of large IWLS'05 and ITC'99 benchmark processors remain undetected after BIST run (42% of stuck-at and 34% of transition faults on average) and thus, BIST logic needs to be tested properly. This paper proposes a hierarchical BIST methodology `HBIST' which uses different BIST techniques to obtain complete stuck-at and transition fault coverage of CUT and then introduces additional levels of BIST logic to test for faults in the BIST logic at the preceding levels. A design methodology is proposed to optimize the number of additional levels of BIST required while keeping the BIST area and power overhead, and the addition of extra faults in BIST logic minimal. Experiments on large benchmarks show an average of 95.9% CUT stuck-at fault coverage (ATPG coverage of 96.4%) and 93.5% CUT transition fault coverage (ATPG coverage of 95.3%) is obtained using HBIST. Also, up to 99.2% (average 93.2%) reduction in external ATE test cost (including cost needed to test additional BIST levels) is obtained using two levels of BIST at 7% average area overhead (compared to scan overhead of 38.2%) and 18% increase in test power.

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

This paper presents a novel test point insertion technique which, unlike the previous ones, is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase a group of test points targeting a specific set of faults is selected. Control points within a particular phase are enabled by fixed values, resulting in a simple and natural sharing of the logic driving them. Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.

In the Reconfigurable System-On-a-Chip (RSOC), an FPGA core is embedded to improve the design flexibility of SOC. In this paper, we demonstrate that the embedded FPGA core is also feasible for use in implementing the proposed hybrid pattern Built-In Self-Test (BIST) in order to reduce the test cost of SOC. The hybrid pattern BIST, which combines Linear Feedback Shift Register (LFSR) with the proposed on-chip Deterministic Test Pattern Generator (DTPG), can achieve not only complete Fault Coverage (FC) but also minimum test sequence by applying a selective number of pseudorandom patterns. Furthermore, the hybrid pattern BIST is designed under the resource constraint of target FPGA core so that it can be implemented on any size of FPGA core and take full advantage of the target FPGA resource to reduce test cost. Moreover, the reconfigurable core-based approach has minimum hardware overhead since the FPGA core can be reconfigured as normal mission logic after testing such that it eliminates the hardware overhead of BIST logic. Experimental results for ISCAS 89 benchmarks and a platform FPGA chip have proven the efficiency of the proposed approach.

A new algorithm for the reseeding of multiple polynomial LFSR for pseudorandom test pattern generation (PRPG) is proposed in this paper. It is based on the Gauss-elimination procedure and the deterministic test set generated by an ATPG software system for combinational circuits. In addition to the general LFSR model, we also provide two further improvements, ms1p and 1smp, to minimize the hardware overhead. Experimental results were obtained on ISCAS-85 benchmark circuits to demonstrate the effectiveness of this methodology. Complete fault coverage is achieved in all circuits. Low hardware overhead is also maintained with a reasonable test length. >

A new algorithm for the reseeding of multiple polynomial LFSR for pseudorandom test pattern generation (PRPG) is proposed in this paper. It is based on the Gauss-elimination procedure and the deterministic test set generated by an ATPG software system for combinational circuits. In addition to the general LFSR model, we also provide two further improvements, ms1p and 1smp, to minimize the hardware overhead. Experimental results were obtained on ISCAS-85 benchmark circuits to demonstrate the effectiveness of this methodology. Complete fault coverage is achieved in all circuits. Low hardware overhead is also maintained with a reasonable test length. >

A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test application time proportionately. Through on-chip decompression, both the number of virtual scan chains visible to the ATE and the functionality of the ATE are retained intact. Complete fault coverage is guaranteed by constructing the decompression hardware deterministically through analysis of the test pattern set.

A definition of operating mode of complex technical object (CTO) concept is introduced. A logical-static interpretation of CTO operating modes is given. A formal grammar of transformations of logical functions for compatibility (incompatibility) of operations in constraints of a static planning model is presented. Transformation rules are introduced for specific cases. An algorithm for formalizing logical multi-mode structures of CTO functioning in static planning terms of operation flows and modes is developed. Results of computational experiments are presented.