Low-latency communication over ATM networks using active messages

The standard procedures for the extraction of gravitational wave signals coming from coalescing binaries provided by the output signal of an interferometric antenna may require computing powers generally not available in a single computing center or laboratory. A way to overcome this problem consists in using the computing power available in different places as a single geographically distributed computing system. This solution is now effective within the GRID environment, that allows distributing the required computing effort for specific data analysis procedure among different sites according to the available computing power. Within this environment we developed a system prototype with application software for the experimental tests of a geographically distributed computing system for the analysis of gravitational wave signal from coalescing binary systems. The facility has been developed as a general purpose system that uses only standard hardware and software components, so that it can be easily upgraded and configured. In fact, it can be partially or totally configured as a GRID farm, as MOSIX farm or as MPI farm. All these three configurations may coexist since the facility can be split into configuration subsets. A full description of this farm is reported, together with the results of the performance tests and planned developments

Digital photography has many advantages over the conventional method. At present commercially available digital ophthalmological imaging systems utilise only a fraction of the advantages of this technique and some of them have fundamental conceptional problems. Images of a fundus camera, a slit lamp and a scanning laser ophthalmoscope were digitised using digital and video cameras and/or frame grabber cards. Digital images and movies were recorded via a personal computer. The image recording software was developed using an imaging library and open source software. The recorded images and video sequences were processed with three different commercially available programme packages. The images were archived in a around-the-clock accessible database. Our digital imaging system is capable to record normal and high resolution slit lamp images, colour fundus images in normal resolution, Fluorescein angiography images in normal and high resolution, digital simultaneous ICG and Fluorescein videoangiograms (without compression) and high resolution macro images. Different functions, e.g., contrast enhancement are integrated in the image capture software. Most of the parameters of the image acquisition are individually adaptable. The digital image archive supports multiple image and video formats. Using standard software and hardware components an imaging system can be constructed featuring functions usually not available in commercial ones. Since the system is adaptable, recording of images with a wide variety of parameters, e.g., for measurements for scientific experiments, is possible.

Low-latency communication over ATM Networks using Active Messages

We present a new tool for the measurement of the non-uniformity of a large-area pulsed solar simulator according to IEC 60904-9. We realized a prototype portable unit that can be controlled via a single USB port of a notebook. The system is composed by several photovoltaic cells and a series of custom designed electronic boards, allowing a high-speed multi-channel sampling of a single pulse. We describe the main components and the design solution, which is using readily available standard electronic and software components, allowing a possible industrialization of the system. Finally we present preliminary results of the prototype unit testing.

Open Systems Software Standards in Concurrent Engineering

Advances in network and processor technology have greatly changed the communication and computational power of local-area workstation clusters. However, operating systems still treat workstation clusters as a collection of loosely-connected processors, where each workstation acts as an autonomous and independent agent. This operating system structure makes it difficult to exploit the characteristics of current clusters, such as low-latency communication, huge primary memories, and high-speed processors, in order to improve the performance of cluster applications. This paper describes the design and implementation of global memory management in a workstation cluster. Our objective is to use a single, unified, but distributed memory management algorithm at the lowest level of the operating system. By managing memory globally at this level, all system- and higher-level software, including VM, file systems, transaction systems, and user applications, can benefit from available cluster memory. We have implemented our algorithm in the OSF/1 operating system running on an ATM-connected cluster of DEC Alpha workstations. Our measurements show that on a suite of memory-intensive programs, our system improves performance by a factor of 1.5 to 3.5. We also show that our algorithm has a performance advantage over others that have been proposed in the past.

Active messages provide a low latency communication architecture which on modern parallel machines achieves more than an order of magnitude performance improvement over more traditional communication libraries. This paper discusses the experience we gained while implementing active messages on the Meiko CS-2, and discusses implementations for similar architectures. During our work we have identified that architectures which only support efficient remote write operations (or DMA transfers as in the case of the CS-2) make it difficult to transfer both data and control as required by active messages. Traditional network interfaces avoid this problem because they have a single point of entry which essentially acts as a queue. To efficiently support active messages on modern network communication co-processors, hardware primitives are required which support this queue behavior The overcame this problem by producing specialized code which runs on the communications co-processor and supports the active messages protocol. Our implementation of active messages results in a one-way latency of 12.3 /spl mu/s and achieves up to 39 MB/s for bulk transfers. Both numbers are close to optimal for the current Meiko hardware and are competitive with performance of active messages on other hardware platforms. >

Commercial cache-coherent nonuniform memory access (ccNUMA) systems often require extensive investments in hardware design and operating system support. A different approach to building these systems is to use Standard High Volume (SHV) hardware and stock software components as building blocks and assemble them with minimal investments in hardware and software. This design approach trades the performance advantages of specialized hardware design for simplicity and implementation speed, and relies on application-level tuning for scalability and performance. We present our experience with this approach in this paper. We built a 16-way ccNUMA Intel system consisting of four commodity four-processor Fujitsu® Teamserver™ SMPs connected by a Synfinity™ cache-coherent switch. The system features a total of sixteen 350-MHz Intel® Xeon™ processors and 4 GB of physical memory, and runs the standard commercial Microsoft Windows NT® operating system. The system can be partitioned statically or dynamically, and uses an innovative, combined hardware/software approach to support application-level performance tuning. On the hardware side, a programmable performance-monitor card measures the frequency of remote-memory accesses, which constitute the predominant source of performance overhead. The monitor does not cause any performance overhead and can be deployed in production mode, providing the possibility for dynamic performance tuning if the application workload changes over time. On the software side, the Resource Set abstraction allows application-level threads to improve performance and scalability by specifying their execution and memory affinity across the ccNUMA system. Results from a performance-evaluation study confirm the success of the combined hardware/software approach for performance tuning in computation-intensive workloads. The results also show that the poor local-memory bandwidth in commodity Intel-based systems, rather than the latency of remote-memory access, is often the main contributor to poor scalability and performance. The contributions of this work can be summarized as follows: • The Resource Set abstraction allows control over resource allocation in a portable manner across ccNUMA architectures; we describe how it was implemented without modifying the operating system. • An innovative hardware design for a programmable performance-monitor card is designed specifically for a ccNUMA environment and allows dynamic, adaptive performance optimizations. • A performance study shows that performance and scalability are often limited by the local-memory bandwidth rather than by the effects of remote-memory access in an Intel-based architecture.

Implementing and debugging high-performance network subsystems is a challenging task. In this paper, we present our experiences from developing and debugging a network interface card (NIC). Our NIC targets networked storage subsystems (Marazakis et al., 2006). For this purpose it mainly provides support for remote direct-memory-access (RDMA) write, sender-side notification of RDMA write completion, and receiver-side interrupt generation. In our work we examine issues that arise during system implementation and debugging, both in terms of correctness as well as performance. We present an analysis of the individual problems we encounter and we discuss how we address each case. For most problems we encounter, it is not possible to rely on existing debugging tools. However, we find that most of the techniques we use in this process, rely on collecting some form of event records from software or hardware components. We believe that such capabilities can be provided for independent hardware or software components in isolation, a fairly straight-forward task, thus, significantly simplifying the debugging process in complex systems of this nature

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

MOPS is a platform for surgical robotics research. It consists of hardware and software components for building surgical robot systems based on existing robot arms. The reference system presented in this paper has two robot arms, each with an adapter for mounting and actuating different types of surgical instruments. Additionally, the system has a high-resolution stereo camera and a simple operator console with haptic devices and foot pedals for teleoperating the manipulators. Software components are based on Robot Operating System (ROS) to keep them modular and reusable for different types of hardware. We evaluate the precision of our system for vision-based tasks and demonstrate its potential for surgical task automation. The mean end-to-end error, including that of the vision system, for a trajectory following task was 1.2mm / 0.3° for one manipulator and 2.7mm / 0.7° for the other. MOPS software and hardware components are made available under an open-source license to encourage collaboration and facilitate the advancement of surgical robotics research.

Introduces queuing network models for the performance analysis of SPMD (single-program, multiple-data) applications executed on general-purpose parallel architectures such as MIMD (multiple-input, multiple data) and clusters of workstations. The models are based on the pattern of computation, communication and I/O operations of typical parallel applications. Analysis of the models leads to the definition of speedup surfaces which capture the relative influence of processors and I/O parallelism and show the effects of different hardware and software components on the performance. Since the parameters of the models correspond to measurable program and hardware characteristics, the models can be used to anticipate the performance behavior of a parallel application as a function of the target architecture (i.e. the number of processors, number of disks, I/O topology, etc.).

Our goal was to investigate the suitability of parallel supercomputer architectures for Quantum Monte Carlo (QMC). Because QMC allows one to study the properties of ions and electrons in a solid, it has important applications to condensed matter physics, chemistry, and materials science. research plan was to Our specific 1. Adapt quantum simulation codes which were highly optimized for vector supercomputers to run on the Intel Hypercube and Thinking Machines CM--5. 2. Identify architectural bottlenecks in communication, floating point computation, and node memory. Determine scalability with number of nodes. 3. Identify algorithmic changes required to take advantage of current and prospective architectures. We have made significant progress towards these goals. We explored implementations of the p4 parallel programming system and the Message Passing Interface (MPI) libraries to run ``world-line`` and ``determinant`` QMC and Molecular Dynamics simulations on both workstation clusters (HP, Spare, AIX, Linux) and massively parallel supercomputers (Intel iPSC1860, Meiko CS-2, BM SP-X, Intel Paragon). We addressed issues of the efficiency of parallelization as a function of distribution of the problem over the nodes and the length scale of the interactions between particles. Both choices influence he frequency of inter-node communication and the size of messages passed. We found that using the message-passing paradigm on an appropriate machine (e.g., the ntel iPSC/860) an essentially linear speedup could be obtained.

The public transport system of New South Wales (NSW), Australia is impotent to receive 100% of the fare from light rail and buses due to the unavailability of a continuous real-time monitoring system. This scheme thereby seeks to help update the NSW public transport ticket collection system, with the aid of a counter that will be integrated into the public transportation within the Ticket Tapping Machine, to provide passenger count against the number of touches occurring at each stop; and thus, increasing the revenue. The product comprises of hardware and software components - the hardware system is located within the public transport while the software system incorporating a web portal is positioned for the authorities to have access to the real-time passenger data. At the hardware end, the ultrasonic sensors and the raspberry pi would detect the number of passengers on the transport and the LCD screen would display the number of passengers who had not tapped their smart card ticket. Additionally, the raspberry pi module used in the hardware component can denote the transportation location with the help of an in-built Wi-Fi component. With this designed technology, the authorities would be able to monitor and record the movements of the passenger in real-time system addressing the existing challenges faced by the NSW public transport authority, especially in the case of light rail and buses being used for free by certain passengers.

Developing a component-bassed software requires verified and standardized software components. This paper presents and approach to build conponent quality assurance process based on process patterns. To describe process patterns, a metamodel is suggested and several process for software components. The process pattern approach was applied to real projects and its advantages and disadvantages are discussed.