Non-Classical Logics

Many-valued logics in general and 3-valued logic in particular is an old subject which had its beginning in the work of Łukasiewicz [Łuk]. Recently there is a revived interest in this topic, both for its own sake (see, for example, [Ho]), and also because of its potential applications in several areas of computer science, such as proving correctness of programs [Jo], knowledge bases [CP] and artificial intelligence [Tu]. There are, however, a huge number of 3-valued systems which logicians have studied throughout the years. The motivation behind them and their properties are not always clear, and their proof theory is frequently not well developed. This state of affairs makes both the use of 3-valued logics and doing fruitful research on them rather difficult.Our first goal in this work is, accordingly, to identify and characterize a class of 3-valued logics which might be called natural. For this we use the general framework for characterizing and investigating logics which we have developed in [Av1]. Not many 3-valued logics appear as natural within this framework, but it turns out that those that do include some of the best known ones. These include the 3-valued logics of Łukasiewicz, Kleene and Sobociński, the logic LPF used in the VDM project, the logic RM3 from the relevance family and the paraconsistent 3-valued logic of [dCA]. Our presentation provides justifications for the introduction of certain connectives in these logics which are often regarded as ad hoc. It also shows that they are all closely related to each other. It is shown, for example, that Łukasiewicz 3-valued logic and RM3 (the strongest logic in the family of relevance logics) are in a strong sense dual to each other, and that both are derivable by the same general construction from, respectively, Kleene 3-valued logic and the 3-valued paraconsistent logic.

The past few decades have seen a resurgence of reasoning techniques in artificial intelligence involving both classical and non-classical logics. In his paper, ``Multi-valued Logics: A Uniform Approach to Reasoning in Artificial Intelligence'', Ginsberg has shown that through the use of bilattices, several reasoning techniques can be unified under a single framework. A bilattice is a structure that can be viewed as a class of truth values that can accommodate incomplete and inconsistent information and in certain cases default information. In bilattice theory, knowledge is ordered along two dimensions: truth/falsity and certainty/uncertainty. By defining the corresponding bilattices as truth spaces, Ginsberg has shown that the same theorem prover can be used to simulate reasoning in first order logic, default logic, prioritized default logic and assumption truth maintenance system. Although this is a significant contribution, Ginsberg's paper was lengthy and involved. This paper summarizes some of the essential concepts and foundations of bilattice theory. Furthermore, it discusses the connections of bilattice theory and several other existing multi-valued logics such as the various three-valued logics and Belnap's four-valued logic. It is noted that the set of four truth values in Belnap's logic form a lattice structure that is isomorphic to the simplest bilattice. Subsequently, Fitting proposed a conflation operation that can be used to select sub-sets of truth values from this and other bilattices. This method of selecting sub-sets of truth values provides a means for identifying sub-logic in a bilattice.

Traditional digital circuits use binary logic for implementation which requires more number of data lines to carry information. In contrast to binary, multiple-valued logic (MVL), digital circuits require less number of data lines to represent information. MVL uses more than two levels to represent a number; thereby reducing the number of interconnects. One of its kind is ternary logic, (known as radix-3 system) and uses three different voltage levels, whereas the other quaternary logic (radix-4 system) uses four different voltage levels to represent a number. Various digital circuits are implemented using MVL which potentially reduces the chip area, power consumption, and propagation delay. This article discusses about fundamental concepts of ternary, quaternary system and reviews some of arithmetic and logic circuits using ternary and quaternary logic. This paper also presents different methodologies used to implement arithmetic and logic operations using MVL. It is found that, due to the effective utilization of interconnects, MVL digital circuits provide better performance over binary digital circuits in terms of area, power, and delay.KeywordsNumber systemArithmetic and Logic circuitsChip areaMultiple-Valued Logic (MVL)Quaternary logicTernary logicTiming delayVLSI

Contemporary critics of two-valued logic concentrate on the reasons for accepting the tertium non datur A V ¬A as a valid propositional schema. Brouwer explicitly states1 that only by unjustified extrapolation of logical principles from those which correctly describe the general relations among propositions on finite domains to those that allegedly regulate propositions on infinite domains, could it happen that A V ¬ A is accepted as valid. He was the first to observe that value-definite (decidably true or false) propositions do not generally transfer value-definiteness to their logical compounds. No better support could be found for the claim that the classical characterization of propositions as entities that are either true or false is inadequate. The union of the class of all true propositions and the class of all false propositions does not contain all logical compounds out of either true or false propositions; it does not contain, for example, certain as yet neither proven nor disproven universal propositions of elementary arithmetic. But nobody has seriously advanced the thesis that such propositions should not count as propositions at all.2 In fact, it is generally conceded that the usual way to form finite and infinite logical compounds makes sense even if nothing can be said about their truth-value.

In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. 
 Keywords: Ternary logic, Ternary logic gates, VHDL language.

The article proposes a method for synthesizing ternary binary logic functions using a multi-threshold element, which significantly extends the capabilities of ternary logic compared to traditional binary logic. The aim of the work is to develop an algorithm for synthesizing ternary logic functions, based on the use of a multi-threshold element, which simplifies the design of logical circuits and reduces energy consumption while maintaining high data processing speed. The study includes a comparative analysis of ternary and binary logic functions, allowing an assessment of the advantages of ternary logic, particularly its ability to process more values than binary logic, which opens up new possibilities for creating more efficient computing devices. Specifically, ternary logic can reduce the complexity of circuits and hardware resource usage, while also enhancing performance in tasks where energy efficiency is critical. An essential part of the research is the development of an algorithm for synthesizing ternary binary logic functions based on a four-threshold multi-valued element. Furthermore, a software module was implemented to automate the synthesis of ternary functions. The program not only generates a graphical representation of the logical circuit but also formulates the analytical expression corresponding to the given logical function. This significantly simplifies the design and analysis of logical systems and enhances the efficiency of computations. Considering the high potential of ternary logic, the results of this work are significant not only for theoretical research but also for practical applications in the development of new computing devices and technologies. The further development of these ideas could contribute to the progress in computational systems working on new principles and open up new possibilities for optimizing technological processes in various fields of science and engineering.

Tremendous amounts of data are being generated and should be processed during the massive employment of artificial intelligence and edge/cloud computing, necessitating computers with higher capabilities. However, as Moore's Law approaches its limit, enhancing computing capability through transistor miniaturization is becoming less feasible. New strategies for “more-than-Moore” are highly preferred to drive future technological advancements. Multiple-valued logic, especially ternary logic with its superior data density compared to traditional binary logic, offers a viable route to augment computing capability while reducing chip interconnections and dynamic power consumption. Despite the growing interest in ternary logic within academia and industry, its practical application remains limited due to the increased transistor count and connections required by earlier logic gate implementations. In this thesis, we present efficient implementation methods of basic ternary logic gates based on emerging nano-electronics including two-dimensional material-based transistors. The fabricated ternary devices show high performance in DC gain and low power consumption. Additionally, compact models of the devices have been established and calibrated, facilitating the circuit design and simulation in Electronic Design Automation (EDA) tools. At the circuit level, this thesis introduces novel ternary arithmetic circuits, including adders and multipliers, that are optimized for low power consumption and minimal delay. Finally, we showcase the practical benefits of ternary logic systems in data processing through the implementation of carry-free arithmetic circuits, underscoring their potential as a transformative computing paradigm.

Quantitative logic in the many-valued logic system are established by Guojun Wang, which is based on linear evaluation lattice frame. In this paper, we defined the truth degree of formulas in 4-valued Godel nonlinear lattice logic system, and we given the basic property of the truth degree. Finally, we introduce the concept of the similarity degree between formulas and logic metric space in 4-valued Godel nonlinear lattice logic. It is proved that the new built concepts are extensions of the corresponding concepts in quantified logic.

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.

The ultimate usefulness of a number system depends on its implementation. Multiple-valued logic has been implemented in charge-coupled devices (CCD). In this technology, logic values are encoded as charge. For example, prototype four-valued logic devices have been implemented at the University of Twente (Enschede, Holland). Hitachi has implemented a 16-valued memory that stores the equivalent of 10/sup 6/ bits. CCD is more compact than any other VLSI technology. Although it is slower than CMOS (complementary metal oxide semiconductor), it is much faster than the disk and has the potential of replacing the disk. The use of multiple-valued logic in CCD increases its storage capacity significantly. Multiple-valued logic has also been implemented in current-mode CMOS.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In terms of memory, multivalued logic can be the fitting logic for the existing binary logic. Ternary logic contains three symbols in place of two symbols used in the binary logic, i.e., 0, 1, 2. More information can be stored with the help of these three symbols. SRAM cell is widely used in the digital circuit. The SRAM cell designed using the ternary logic can be used in the design of large memory arrays designed using ternary logic. The traditional ternary inverter which is used in the design of the traditional ternary SRAM cell is unable to store the proper values for the second state, there is a voltage level drop, which in turn affects the data read/write value of the SRAM cell designed using this traditional ternary inverter. Hence there is a need to design the ternary inverter cell which can give the proper output voltage level of all three states of the ternary logic. The level shift ternary inverter is designed to fulfill this disadvantage. The ternary inverter is designed in order to achieve the ideal DC characteristics, and the same level shift ternary inverter is used in the design of level shift ternary SRAM. This ternary SRAM stores the data properly at read/write signal. The traditional ternary inverter and traditional ternary SRAM, level shift ternary inverter and level shift ternary SRAM are implemented in Cadence 45 nm technology. The traditional ternary inverter consumes 2.37 μW power, and the level shift ternary SRAM consumes 2.43 μW power. The traditional ternary SRAM consumes 3.012 μW and level shift ternary SRAM consumes 3.14 μW. At the cost of a little bit increased power and the number of transistors, the traditional ternary SRAM can be replaced with level shift ternary SRAM. This level shift ternary SRAM stores all the voltage levels at all three levels. The same level shift ternary SRAM cell can be used for the design of large memory arrays.

A ternary logic system to realize the simplest multivalued logic architecture can enhance energy efficiency compared to a binary logic system by reducing the number of transistors and interconnections. For the ternary logic system, a ternary logic device to harness three stable states is needed. In this study, a vertically integrated complementary metal-oxide-semiconductor ternary logic device is demonstrated by monolithically integrating a thin-film transistor (TFT) over a transistor-based threshold switch (TTS). Because the TFT and the TTS have their own source (S), drain (D), and gate (G), there are physically six electrodes. But the hybrid ternary logic device of the TFT over the TTS has only four electrodes: S, D, GTFT, and GTTS like a single MOSFET. It is because the D of the underlying TTS is electrically tied with the S of the superjacent TFT. By combining an on- and off-state of the TFT and the TTS, ternary logic values of low current ("0"-state), middle current ("1"-state), and high current ("2"-state) are realized. Particularly, static power consumption at the "1"-state is decreased by employing the TTS with low off-state leakage current compared to previously reported other ternary logic devices. In addition, a footprint of the ternary logic device with the vertically overlaying structure that has a framework of "one over the other" can be lowered by roughly twice compared to that with the laterally deployed structure that has an organization of "one alongside the other".

Advances in multiple-valued logic (MVL) have been inspired, in large part, by advances in integrated circuit technology. Multiple-valued logic has matured to the point where four-valued logic is now part of commercially available VLSI IC's. Besides reduction in chip area, MVL offers other benefits such as the potential for circuit test. This paper describes the historical and technical background of MVL, and areas of present and future application. It is intended, as well, to serve as a tutorial for the nonspecialist.

In this paper we present a many-valued logic programming, based on reinterpreted Belnap's 4-valued bilattice: we introduce the new semantics for a 4-valued implication by relative pseudo-complement, used for intuitionistic logics. This kind of logic programming is particularly useful for data integration with possibly incomplete and inconsistent information. We define an ontological encapsulation of the epistemic many-valued logic programs with negation, based on this bilattice, into 2-valued meta logic programs. Obtained 2-valued logic semantically reflects original epistemic many-valued logic, and can be used in order to define many-valued logic entailment and inference closure for many-valued truth assignments.

This paper presents addition and multiplication in Galois field using multi-valued logic. Multi-valued logic (MVL) has matured to the point where four-valued logic is now part of commercially available VLSI IC’s. Modulo-4 addition and multiplication is also presented in this paper. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice