4 bit adder Research Articles (Page 1)

A comprehensive analysis of the impact of sub 10-nm CNFET technology on 64-bit parallel prefix adders and 32-bit matrix multiply units

The adder is a fundamental logic block in most digital processing systems, but it is also a significant source of power consumption due to its high switching frequency. This paper presents the application of the Clock Enable (CE) technique to reduce dynamic power in a 32-bit adder implemented on FPGA. Instead of directly gating the clock signal, the input and output registers of the adder are controlled by the CE signal, maintaining their values when the adder is inactive. Experimental results on a Spartan-3E FPGA show that dynamic power is reduced by approximately 58.6%, total power decreases by 36.6%, and junction temperature drops by 2°C compared to the conventional design. This technique is simple, easy to integrate, and provides significant benefits for low-power digital design.

Abstract The scaling of metal oxide semiconductor field effect transistor (MOSFET) causes many limitations in current scaled technology nodes. The secondary effects limit the application of MOSFETs in nanoscaled logic circuits. Many alternative ways are suggested for the innovation of new technological developments. Quantum-dot cellular automata (QCA) nanotechnology is getting key attention in the current scenario due to the ability of fast, power- and area-efficient implementations of the logic circuits. The exclusive OR (XOR) gate is the basic building block of many logic applications. Hence, this paper proposes an optimized novel structure of a 3-input XOR (XOR3) gate, which is successfully verified for the logic designs of a 4-bit parity generator, a 4-bit full adder, and a 4-bit binary to gray code converter. The proposed XOR3 gate consists of 8 QCA cells only and 2 clock phases. The reliability concern in terms of fault-tolerant analysis for the proposed XOR3 gate is also presented in the paper. The proposed designs are compared with the existing designs and show the improved performance metrics. The QCA Designer-E tool is used for circuit simulations. The energy dissipation values are estimated using the QCA Designer-E and the QCA Pro tools. The proposed XOR3 gate, 4-bit parity generator, 4-bit full adder, and 4-bit binary to gray code converter save a total of 20%, 26.32%, 26.40%, and 17.24% of cells, respectively, in comparison with the best-reported similar design.

A new proposal of an all optical 2-bit adder based on 2D photonic crystal ring resonators

Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder

A breakthrough in in-memory computing technologies hinges on the development of appropriate material platforms that can overcome their existing limitations, such as larger than optimal footprint and multiple serial computational steps, with potential accumulation of errors. Using a molecular switching element with multiple non-monotonic and deterministic transitions, the device count and the number of computational steps can be substantially reduced. With molecular materials, however, the realization of a reliable and robust platform isan unattained goal for decades. Here, crossbar arrays with up to 64 molecular memristors are fabricated to experimentally demonstrate 8-bit serial and 4-bit parallel addersthat operate for thousands of measurement cycles with an estimated error probability of 10-16 . For performance benchmarking, a 32-bit parallel adder is designed and simulated with 268million inputs including contributions from the peripheral circuitry showing a 47× higher energy efficiency, 93× faster operation, and 9% of the footprint, leading to 4390 times improved energy-delay product compared to a special purpose complementary metal-oxide-semiconductor (CMOS)-based multicore adder.

Early RTL delay prediction using neural networks

Conventional CLA adder has has a large number of transistors and high input impedance, which affects various performance aspects, resulting in high delay and power consumption. Therefore, to increase the performance and reduce delay, several optimized structures of CLA are proposed. From the perspective of structure and power, this paper selects four different design schemes and uses Cadence Virtuoso 90nm technology to compare and analyze the optimization results in aspects of circuit area, delay and power consumption. The analysis results show that the conventional 4-bit adder structure can be improved by designing the carry term Field Effect Transistor (FET) network and replacing the existing gate circuit with a hybrid Gate diffusion technology (GDI) gate, which can reduce the number of transistors and the design circuit area. They also contribute to improving the power consumption, delay, power delay product (PDP) and other performance parameters. Pipeline technology and multi-layer CLA block technology are suitable for carry look-ahead adder with more bits and longer carry chain, which can shorten carry propagation time, further optimize processor performance and improve CPU computing efficiency.

The adder is the maximum usually used mathematics block in programs inclusive of <span lang="EN-US">central processing unit (CPU) and virtual sign processing. As a result, it is important to expand a space-saving, low-strength, high-overall performance adder circuit. The hassle is diagnosed to layout mathematics sub structures with minimized strength dissipation, low area, and minimal time postpone of common-sense circuits. In conventional <a name="_Hlk95894088"></a>carry select adder (CSA), the time required to generate the sum output is less than other basic adder circuits but the principal difficulty is the location because the variety of transistors used to put in force the CSA circuit is fairly more. So, the area increases because of which the overall power consumption of the circuit will be more. If it's far viable to lessen the variety of transistors used withinside the structure of CSA adder, then, the strength intake of the circuit may be decreased or even the reaction time will improve. By lowering the area of the adder circuit, the suggested solution intends to reduce power consumption and latency.</span>

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Skyrmion-based devices are an attractive candidate for nonvolatile memory and low-power computation. In a real device, however, skyrmions easily annihilate at device edges, which hampers device applications. Here, we present a novel skyrmion-based logic device, which takes advantage of the skyrmion annihilation (SA) and increases the efficiency of logic operation. An SA half adder (HA) is implemented in a ferromagnet/heavy metal nanotrack by introducing a geometric notch that annihilates the skyrmion. In addition, full adder and n-bit SA ripple-carry adder are demonstrated by directly cascading the SA HAs. The prototype of a 32-bit SA ripple-carry adder consumes energy as low as 0.62 pJ per each operation, which is only 18% of the previously proposed skyrmion adder. Our SA logic gate can, therefore, be a promising candidate for the beyond-CMOS logic device.

A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding

This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

This paper presents possible designs for high speed error tolerant adder using Gate Diffusion Input (GDI) technique. The 1-bit modified full adder (MFA) proposed in [1] is implemented using GDI technique (GDI-MFA). The GDI-MFA is extended to implement a 16-bit high speed error tolerant adder (GDI-HSETA). The performance of various configurations is studied based on metrics such as delay, area and power dissipation. The circuits have been simulated using pSPICE software. From the results it is observed that the proposed GDI-MFA has 52% less transistor count and consumes 33% less power compared to conventional adders. Results of simulation of GDI-HSETA and other adders in pSpice indicate that the proposed adder has 21.6% power reduction and 13% less transistor count. Also, based on the implementation of GDI-HSETA and existing 16-bit adders on FPGA Spartan 6 platform, it is observed that GDI-HSETA achieved power reduction compared to 16-bit adders using conventional design.

Adiabatic quantum-flux-parametron (AQFP) logic is a very energy-efficient superconductor logic due to zero static power dissipation and adiabatic switching operation. However, there is a shortage of electronic design automation (EDA) software tools adaptable to AQFP logic. Such tools are essential for designing large-scale-integration circuits efficiently. Therefore, we have developed a first set of EDA tools that handle cell placement and wiring, written in SKILL, the Cadence scripting language. Our tools also consider the maximum wire length constraint that exists in AQFP logic. First, AQFP logic cells are repositioned via the genetic algorithm to minimize the number of wires that violate the wiring length constraint. Buffers are then automatically inserted as signal repeaters for logic rows where the violations still exist. We then complete the logic wiring of the circuit using the channel routing algorithm. We demonstrate the usability of the EDA tools by designing a 16-bit adder as well as a randomly generated test circuit.

By now, there have been many demonstrations of resistive switching (“memristive”) devices based on organic, chalcogenide, transition metal-oxide and silicon materials and involving different physical switching mechanisms, such as phase-change transitions and modulation of the ionic concentration profiles by electrical and/or thermal forces. The conductance of some properly engineered memristors can be continuously tuned with relatively large electrical bias, and retained, effectively indefinitely, when small stress is applied. Such analog nonvolatile memory functionality combined with potentially very high device density, achieved by lateral scaling and/or monolithical vertical integration, enable many new exciting applications of memristors in neuromorphic and other types of computing. In my talk, I will review several such applications based on metal-oxide memristors which were a recent focus of my group. I will start with stateful material implication logic, which was originally suggested by HPL group. In our work, we showed that 3D version of this logic allows resolving Feynman grand challenge of implementing 8-bit adder in a volume smaller than 50-nm cube. I will then review our experimental work on memristor-based security primitives, in which we utilized device variations and their nonlinear I-Vs to demonstrate functionality and physical performance superior to those of conventional approaches. Finally, I will discuss Race Logic, a novel computing paradigm in which information is encoded in timing of the signals, so that a particular problem is mapped to a circuit with controllable memristor-based delay elements, and the solution is provided by measuring the time for the injected signals to propagate via circuit. Due to direct encoding of the computation to the underlying physics, Race Logic is extremely energy efficient for a variety of problems, such as bioinformatics and neurocomputing. I will conclude my talk with a summary on the device/material challenges, and potential future work, specific to the discussed applications.

Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

ABSTRACTThis paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.