ASML (Netherlands)

Quasi-bound states in the continuum in dielectric metasurfacessupport sharp Fano resonances that emerge from the interference betweenbrightand dark modes. We exploit this modal interplay to demonstrate tunablethird-harmonic emission, controlled through the driving pulse’swavelength and intensity. Our experiments show imbalances in third-harmonicdiffraction patterns and non-Gaussian third-harmonic spectral featuresthat exhibit strong variations near the Fano resonance. We explainthe observations via a coupled-oscillator model that captures theinterplay between the driving field and the nonlinear response ofthe modes, explaining our observations and providing a predictiveframework for optimizing the third-harmonic diffraction efficiency.These results establish pulse-engineered metasurfaces as a powerfulplatform for nonlinear wavefront shaping and frequency conversionapplications while simultaneously serving as a warning that pulseproperties play a vital role in metasurface function design.

The High-NA EUV EXE platform introduces cost-effective shrink for future device nodes with key design changes like 0.55NA projection optics, anamorphic demagnification, and central obscuration. Over the past year, the EXE:5000 proto system in Veldhoven and customer fabs have shown impressive resolution, global and local CDU, and dose reduction, validating the designed contrast and resolution improvements. The main challenge is achieving sufficient Depth-of-Focus (DoF) for focus margin. This presentation highlights key imaging achievements and addresses the High-NA DoF challenge, discussing pattern transfer in resist and evaluating DoF enhancement techniques like pupil-mask-wavefront co-optimization and micro focus drilling

EUV reflectometry was used to study the multilayer structure of several test masks, on areas with and without TaBN absorber. For interpretation of the data we propose an updated multilayer mask model with oxide layers on- and below the capping layer, and a genetic fitting algorithm was used for layer thickness optimization. The updated model yields improved goodness-of-fit to the EUV reflectance data, and indicates the presence of SiO₂ and RuO₂ layers in the capping layer stack. Moreover, fits to the EUVR data for the absorber pad indicate that the TaBO layer on top of the absorber is significantly thicker than nominal. CS-TEM measurements showed the TaBO to be present on the absorber sidewalls as well. Wafer exposures of dense line features through pitch (P28-P40) were performed using the same set of test reticles. The nominal mask model was found to strongly underpredict pupil induced contrast fading and best focus shifts. The updated mask model predicts a 2x stronger pupil induced contrast fading and 1.5x larger best focus range through pitch, hereby removing the main discrepancies between wafer data and simulations. This result emphasizes the importance of mask characterization measurements for derivation of an accurate mask model for imaging simulations.

Designing next generation distributed CyberPhysical Systems (dCPS) requires effective Design Space Exploration (DSE) methods to evaluate system design alternatives and their impact on performance. While existing DSE approaches focus on hardware optimization and software-to-hardware mapping, they often overlook parallel execution opportunities within software tasks. Current application workload models for complex dCPS assume fixed execution orders, limiting the ability to explore and exploit software parallelism. To address this issue, we propose refined workload models derived from execution traces that capture both inter- and intra-process dependencies. Building on these models, we present a method to identify tasks that can be safely reordered or executed in parallel without modifying the existing software implementation. We validate our approach through a case study on the ASML Twinscan lithography machine, demonstrating measurable performance improvements without impacting the system functional correctness.

Fano lineshapes associatedwith quasi bound-state-in-the-continuumresonances, that are supported by dielectric metasurfaces, have theadvantageous properties of being extremely sensitive to minute geometricalchanges in the meta-atoms. We show an approach to determine deep subwavelengthfeature sizes, comparable to semiconductor critical dimension metrology,by structurally infilling a void of a dielectric disk-hole metasurfacedesign. Our simulated results show a sensitivity of 40.5 nm resonantwavelength shift for a 1 nm feature width (i.e., critical dimension)change, at an optical line width of 1.8 nm. We present both experimentaland simulated results of different void infillings and attribute thespectral change of the resonance to the sensitivity to an effectiveindex in the void of the meta-atom, which arises from the filled volumefraction and the material boundaries orientation relative to the localpolarization. Treating our metasurface as an effective index sensor,the sensitivity is 262 nm·RIU–1 and the figureof merit is 146 RIU–1, which underlies the pronouncedresonant wavelength shift driven by similarly large changes in theeffective index caused by extremely tiny critical dimension variations.This approach could impact critical dimension measurements in semiconductormetrology, as it works at the high throughput of optical measurementswhile performing at the high resolution of scanning electron microscopy.

Abstract Cryogenic Pulsating Heat Pipes (PHPs) offer a promising alternative as efficient thermal connection between cryocoolers and superconducting elements. Addressing this, the Paul Scherrer Institute (PSI), in collaboration with VDL Enabling Technologies Group (VDL ETG), has initiated a project to develop and assess cryogenic PHPs tailored for superconducting applications. This paper introduces a new experimental setup for cryogenic PHP characterization. It outlines the design, instrumentation, and operational procedures of a vertically oriented 20-tube neon PHP. The results of experiments with this PHP, for a condenser temperature of 27.1 K, are compared with those of another group in similar conditions. The minimal thermal resistance reached is 0.14 K/W and the maximal heat power transferred is 22 W. These results provide encouraging evidence of the system’s potential for cooling high-temperature superconducting coils.

Strong trends drive the semiconductor industry: ubiquitous computing, the energy transformation and artificial intelligence, to name just a few, have the potential to propel the industry towards $1 trillion of sales by 2030. Enabling this trajectory is the extension of Moore’s Law through innovation in semiconductor devices, materials, manufacturing technologies and 3D integration. To enable chip makers in their pursuit of more powerful, smaller, cheaper, more integrated and more energy-efficient chips, ASML focuses on driving a holistic lithography roadmap with innovation across the entire product and service portfolio. At the core of it is EUV lithography technology. EUV is now mature, and the roadmap offers further improvements in imaging performance, accuracy and productivity, as well as a major reduction in cost per wafer. EUV technology must however be complemented with a large suite of lithography, metrology and process control applications to optimize cost and performance. In 2024, ASML has shipped several High NA EUV systems and is enabling customers to prepare High NA insertion by supporting its customers’ R&D with those systems, as well as in its High NA lab in Veldhoven, the Netherlands. The new High NA optics, combined with progress on the EUV source, provide the foundation for the future of EUV in the form of a common platform, capable of carrying 0.33 NA, 0.55 NA and 0.75 NA and providing a significant cost reduction opportunity. Our progress on multi-beam, wafer bonding process control and DUV lithography for advanced packaging are the other critical elements ASML is providing in support of Moore’s Law. ASML is committed to push technology to new limits, partnering with all members of our ecosystem, to enable chip makers to realize their ambitions.