3-8 多数の比較器を用いた可変長復号回路の設計自動化(第3部門符号化・復号化)

In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 mum process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.

Variable-length code (VLC) is the most popular data compression technique. Therefore, a high throughput variable-length decoder (VLD) is required in many applications. In this paper, we propose two simple modified methods which can increase throughput of memory-based two-bit structure variable-length decoder system. The additional hardware of the modified architecture is a control unit and some memory space. The overall system still consists of control unit, arithmetic unit and memory. Simulation results show that the decompression rate based on 0.6 um CMOS process and MPEG2 coding table-15 can achieve 720 M bits/s with 100 MHz clock rate.

This paper presents a low-power variable length decoder exploiting the statistics of successive codewords. The decoder employs a small look-up table working as a fixed cache to reduce the number of activations of a variable length code detector where most power is consumed. The power simulation results estimated with Powermill show that 35% energy is reduced on the average compared with the previous low-power scheme.

We introduce Fine Grain Scheduling (FGS) as a post-processing step to circuits classically designed as a data-path controlled by a finite state machine (FSM). Such circuits may have timing errors, particularly if they are generated by High Level Synthesis (HLS) tools that make use of crude temporal estimates during scheduling. FGS reschedules the FSM to ensure correct execution at a requested frequency on the data-path.The proposed algorithm takes into account all the electrical constraints of the data-path, namely propagation times, set-up and hold times of memorization elements, and even delays due to the interconnects if the data-path is placed and routed. Like HLS algorithms, FGS supports multi-operators cells, multi-cycle operators and chaining. However, it also makes use of mutli-cycles chaining to allow the chaining of several operators over several cycles without intermediate memorizations.Experimentation of FGS on an MPEG2 Variable Length Decoder and a full MJPEG decoder has demonstrated that the approach is particularly well suited for the design of asynchronous coprocessors. Synchronous processors cannot be scheduled by FGS because the inputs and outputs dates are modified.

System-level designers typically rely on white-box detailed descriptions of embedded systems in order to perform their design choices and optimisations. The white-box approach assumes that the complexity of the system can be managed by decomposing the global system into a set of simple and well-described components. This assumption is generally not true when non-linear interactions happen between the different subsystems. This paper explores, as an alternative, a black-box modelling methodology based on intelligent data analysis in order to support system-level designers in characterising the performance of embedded applications. The rationale behind this approach is that nowadays the designer can easily store large amount of data related to the system, and consequently discover relevant information by analysing them in a black-box fashion. As a case study, we address the performance modelling of software applications running on an embedded microprocessor. We introduce a data analysis method which, on the basis of a high-level characterisation of the software functionality and the hardware architecture, is able to predict the number of execution cycles on a embedded processor. We propose the adoption of a local learning technique (lazy learning), which proved already to be effective in previous works, to model the unknown input/output relation between the hardware/software parameters of the application and the number of execution cycles. Experiments with standard computational code (sorting, mathematical computation) and with a specific streaming algorithm for MPEG variable length decoding are presented to support this claim.

An improved implementation scheme for AVS entropy decoding based on FPGA is proposed in this paper. The additional control circuit is used to get rid of the code streams parsed every cycle without adding any parsing periods. And it makes the barrel shifter prepositive so as to balance the time sequence path in the front end. In this way, the deficiency in the traditional structure of variable length decoding is conquered. Compared with the traditional structure, the proposed scheme achieves 43.2 percent time sequence improvement at the cost of 2.5 percent LE and the real-time high-definition (4:2:2) video decoding sequence can be implemented on Cyclone II EP2C35F672C6.

This paper explores the role of data analysis methods to support system-level designers in characterising the performance of embedded applications. In particular, we address the performance modelling of software applications running on an embedded microprocessor. We propose a data analysis method, which, on the basis of a parameterisation of the software functionality and the hardware architecture, is able to predict the number of execution cycles on an embedded processor. Experiments with standard computational code (sorting, mathematical computation) and with MPEG variable length decoding are presented to support this claim.

We present the multiple variable length decode algorithm implemented in most video applications on MDSP. In our implementations we were able to decode multiple symbols per cycle. The implementation is efficient and is targeted towards memory constrained embedded systems. We have confirmed this algorithm in our implementations of H261/3, MPEG2/4 and achieved multifold speedup improvements against algorithms which can decode at the symbol rate only. This limits the decoding throughput capability of these algorithms. Most parallel decoding approaches use the length of the first codeword to detect the second codeword in parallel. By a single table lookup operation we detect multiple codewords without any detection mechanism.

This paper gives a description of our real-time software MPEG-4 video decoder. The performance of the decoder and the fast algorithms used for real-time decoding are discussed. Our techniques used to speed up four computationally intensive modules, inverse discrete cosine transform, context-based arithmetic decoding, padding, and variable length decoding, are also presented in this paper. Our decoding speed is improved so that software real-time video decoding is possible.

With continuing progress in VLSI and ASIC technologies, digital signal processing (DSP) algorithms have continued to find great use in increasingly wide application areas. DSP has gained popularity also in embedded systems although these systems set challenging constraints for implementations. Embedded systems contain limited resources, thus embedded DSP systems must balance tradeoffs between the requirements on computational power and computational resources. Energy efficiency has been important in batterypowered devices, but nowadays also the limited heat dissipation in small devices calls for low-power consumption. Successful implementation of DSP applications in embedded systems requires tailoring, which in turn sets challenges for design methodologies. For this special issue, we received 14 submissions and a collection of seven papers was finally accepted. The special issue is opened by “Observations on power-efficiency trends in mobile communication devices,” where the authors O. Silven and K. Jyrkka analyze the power consumption in the current mobile communication devices. Several bottlenecks in the current implementation style have been identified, thus the paper provides a good motivation for the following papers. In “The Sandbridge SB3011 platform,” the authors John Glossner et al. describe a system-on-a-chip (SoC) multiprocessor targeted as a software-defined radio platform. The platform provides solutions to the challenges in future mobile devices given in the previous paper. “A shared memory module for asynchronous arrays of processors” authored byMichael J. Meeuwsen et al. considers also chip multiprocessors. The presented shared memory module can be used for interprocess communication or to increase application performance by parallelizing computation. In “Implementing a WLAN video terminal using UML and fully automated design flow” by Petri Kukkala et al., an automated design flow for multiprocessor SoC is presented. The flow is based on UML descriptions and the authors demonstrate their design flow with a design case. Programming of chip multiprocessor platforms is considered in “pn: a tool for improved derivation of process networks” by Sven Verdoolaege et al. The paper discusses conversion of sequential programs to process networks allowing optimization of communication channels and buffers. In “A SystemC-based design methodology for digital signal processing systems,” the authors Christian Haubelt et al. describe a design flow for SoC designs containing automatic design space exploration, performance evaluation, and automatic platform-based system generation. The design flow is based on SystemC descriptions and the presented tools can automatically detect the underlying model of computation. Application-specific implementations are often used to speedup certain DSP tasks in embedded systems. In “Priority-based heading one detector in H.264/AVC decoding,” the authors Ke Xu et al. consider such implementations to speed up video decoding applications. The authors present a low-power decoder implementation for context-adaptive variable length coding defined in H.264 standard.