Hardware-software co-designing benchmark-driven superpipelined instruction set processors

Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design space and the time required for detailed cycle-accurate simulations. The proposed design framework takes as inputs the design targets (upper bounds on execution time, area, and energy), design alternatives, and one or more application programs. The output is the set of out-of-order superscalar processors that are Pareto-optimal with respect to performance-energy-area. The core of the new design framework is made up of analytical performance and energy activity models, and an analytical model-based design optimization process.For a set of benchmark programs and a design space of 2000 designs, the design framework arrives at all performance-energy-area Pareto-optimal design points within 16 minutes on a 2 GHz Pentium-4. In contrast, it is estimated that a naive cycle-accurate simulation-based exhaustive search would require at least two months to arrive at the Pareto-optimal design points for the same design space.

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set.

The authors propose a synthesis methodology for high-performance pipelined instruction set processors. Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of the Advanced Design Automation System (ADAS) which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is to perform pipeline scheduling with any fixed instruction-latency, and generate a reorder table for a back-end compiler to resolve potential pipeline hazards existing in the design. Models for performance and cost of both hardware and software are developed to characterize the design space. A synthesis example of a simple instruction set processor illustrates Piper's synthesis capabilities and how the performance and cost of hardware and software are estimated. >

Speculative execution is an important source of parallelism for VLIW and superscalar processors. A serious challenge with compiler-controlled speculative execution is to efficiently handle exceptions for speculative instructions. In this article, a set of architectural features and compile-time scheduling support collectively referred to assentinel schedulingis introduced. Sentinel scheduling provides an effective framework for both compiler-controlled speculative execution and exception handling. All program exceptions are accurately detected and reported in a timely manner with sentinel scheduling. Recovery from exceptions is also ensured with the model. Experimental results show the effectiveness of sentinel scheduling for exploiting instruction-level parallelism and overhead associated with exception handling.

Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this paper, we use EEMBC, an industrial benchmark suite, to compare the VIRAM vector architecture to superscalar and VLIW processors for embedded multimedia applications. The comparison covers the VIRAM instruction set, vectorizing compiler and the prototype chip that integrates a vector processor with DRAM main memory. We demonstrate that executable code for VIRAM is up to 10 times smaller than VLIW code and comparable to /spl times/86 CISC code. The simple, cache-less VIRAM chip is 2 times faster than a 4-way superscalar RISC processor that uses a 5 times faster clock frequency and consumes 10 times more power VIRAM is also 10 times faster than cache-based VLIW processors. Even after manual optimization of the VLIW code and insertion of SIMD and DSP instructions, the single-issue VIRAM processor is 60% faster than 5-way to 8-way VLIW designs.

Table lookups are one of the most frequently-used operations in symmetric key ciphers. Particularly in the newer algorithms such as the advanced encryption standard (AES), we frequently find that the greatest fraction of the execution time is spent during table lookups, varying between 34% and 72% for the five representative ciphers we consider: AES, Blowfish, Twofish, MARS, and RC4. In order to accelerate and parallelize these table lookups, we describe a new parallel table lookup (ptlu) instruction. Our synthesis results indicate that such an instruction can be added to a basic RISC processor with no cycle time impact. We compare the performance of the ptlu instruction with the speedups available through more conventional architectural techniques such as multiple-issue execution. We find that the performance benefits of using the ptlu instruction can be far higher than increasing the number of instructions executed per cycle in superscalar or VLIW processors.

This paper describes a purely software-based approach to handle permanent faults in the data path of a statically scheduled superscalar processor architecture; e.g. a VLIW processor. This approach does not need any hardware in the processor core itself to reconfigure the data path. Rather the reconfiguration is done in software by modifying the binary code in the program memory of the processor. By this, the usage of a faulty component in the data path can be avoided during the execution of the program. The modification of the program is carried out by a repair routine that is executed by the faulty processor itself. It is shown that this is possible even if there is a fault in the data path. The modification of the binary code takes place immediately after a software-based self-test. Both, the self-test and the modification are carried out immediately after the start-up of the system. Thus, the detection and repair of a fault can happen in the field. Furthermore, the compiler must generate the program in a special way in order to guarantee that the binary code can be modified under all specified fault situations. A simple scheduling algorithm that produces such fault-tolerant binary code is presented, too.

The simulation of parallel computers is discussed. In particular, a technique, called cross-profiling, that can be used to improve the efficiency of these simulations substantially is presented and evaluated. Cross-profiling, along with another simulation technique called execution-driven simulation, can be used to simulate one processor's instruction set (the target processor) with another processor that has a different instruction set (the host processor). Moreover, this technique is significantly faster than the usual method where several host instructions are executed to emulate the effect of executing a single instruction of the target processor. The cross-profiling technique is introduced, and it is shown how it can be combined with execution-driven simulation. The results of several experiments that demonstrate that the error introduced by cross-profiling is typically less than 1% are presented. >

A method for the identification of stuck-at bits on a data bus is described. Faulty data words are compared to isolate the stuck-at bits. A similar method can be used to identify an instruction which does not execute correctly in a processor instruction set. Here, faulty programmes, or faulty programme segments, are compared to isolate the faulty instruction. For both bus and instruction fault cases, probabilistic analyses are given with explicit formulas and data for the mean number of faulty samples required for diagnosis, and also the associated standard deviation. Both of these procedures use on-line data and are suitable for the diagnosis of intermittent faults.

Checking a page's accessibility (not mapped, read only or read/write) is sometimes useful for operating system kernels. We describe a technique for extending a processor's instruction set (by software) so that accessibility tests can in most cases be done faster than parsing the page table tree by software.

An explicitly declared delayed-branch mechanism for a superscalar architecture

Application-specific extensions of a processor provide an efficient mechanism that meets the growing performance and power demands of portable embedded applications such as interactive multimedia communications. This work investigates the use of both the luminance and chrominance components in color image- and video-processing applications and proposes a color-aware instruction set extension (CAX) that improves the performance of color multimedia-processing applications. The CAX ISA is able to exploit a new level of subword parallelism not reachable by current multimedia extensions. Unlike typical multimedia extensions (e.g., Intel MMX, MIPS MDMX, and AMD 3DNow!), CAX instructions support parallel operations on two-packed 16-bit (6:5:5) YCbCr color pixels in a 32-bit datapath width and obtain substantial performance and code density improvements through direct support for color data processing rather than depending solely on generic subword parallelism. The results on a set of media benchmark applications indicate that the CAX versions achieve a speedup ranging from 3x to 5.8x while reducing energy consumption from 68% to 83% over the baseline versions on an identically-configured, dynamically-scheduled superscalar processor. The CAX versions also outperform the MDMX (MIPS multimedia extension) performance.

12 - The next generations

It's like building a bridge. Once the main lines of the structure are right, then the details miraculously fit. The problem is the overall design. Freeman Dyson in Freeman Dyson: Mathematician, Physicist, and Writer, Interview with Donald J. Albers, The College Mathematics Journal, 25, No. 1, January 1994 . Now that we have been introduced to the fundamentals of Verilog, we make a slight change in course to return to the top level of the design flow shown previously in Figure 1.2. In particular, we now discuss the process by which we define the instruction set of a new processor. The instruction set architecture (ISA) of a processor defines all of the instructions available in the processor plus the storage elements that are accessible to the assembly language programmer. The contents of these storage elements, plus a few more that may not be directly accessible to the programmer, comprise the processor's state . In this chapter, we show how the ISA of a complete processor, which we call the Very Small Processor Architecture , or VeSPA for short, is defined, refined, and ultimately specified. This processor is quite simple, with only slightly more than a dozen instructions. However, it is a complete processor capable of executing programs written in a high-level language compiled with an appropriate compiler. We use this processor throughout the remainder of this text as a vehicle for demonstrating the entire processor design process when using the Verilog hardware description language. Instruction set design The design of an instruction set for a new processor is more of an art than a science.