None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.

This paper presents design of an ultra-high precision bandgap voltage reference circuit in a 180nm BCDMOS 1P6M process. A novel current trimming technique is introduced to achieve high accuracy and low temperature coefficient. This bandgap voltage reference circuit achieves a low 17.1ppm temperature coefficient in measurement and 0.15% 3σ inaccuracy in simulation after trimming at 1.19V over temperature range of −40 to 125°C.

ABSTRACTThis paper proposes a nanowatt voltage reference (VR) with temperature coefficient compensation. All transistors work in the subthreshold region. The complementary‐to‐absolute‐temperature (CTAT) voltage and proportional‐to‐absolute‐temperature (PTAT) voltage are mainly generated by two NMOS transistors with different threshold voltages. At the same time, a simple temperature compensation circuit is designed to optimize the temperature coefficient at high temperatures, so that the proposed VR circuit can generate a reference voltage with a wider temperature range and a lower temperature coefficient. The proposed VR circuit is implemented using a standard 0.18‐μm CMOS process with an active area of only 0.022 mm2. The postlayout simulation results show that the proposed VR circuit generates a reference voltage of 308.21 mV at room temperature. Its temperature coefficient is 6.4 ppm/°C over a temperature range of −40°C°C–140°C, with a power consumption of 7.4 nW. The voltage line sensitivity (LS) is 0.098%/V, and the power supply ripple rejection (PSRR) is −72 dB @DC and −42 dB @10 MHz.

Studies on use of lead iron tungstate-lead titanate relaxor binary system as a pressure sensing material

In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variation at the same time.

A curvature-compensated CMOS voltage reference using [formula omitted] characteristics

This paper presents a high-precision, low temperature coefficient (TC) CMOS bandgap reference for high-performance multi-channel ADC working under wide temperature range. A piecewise curvature compensation technique is proposed to extend its operating temperature range and keep its low temperature coefficient. A s-compensation technique is used to cancel the PTAT and non-PTAT spread of the output due to variation of β in the BJTs. Moreover, the trimming resistors are implemented to calibrate the 1st-order temperature coefficient and absolute value of the output voltage. The bandgap reference designed in 0.18μm CMOS process has a super low temperature coefficient of 2.1ppm/°C over a wide temperature of −55 ° C to 140 ° C, making it appropriate to provide reference voltage for a high-precision ADC.

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35 µm CMOS process demonstrate that a temperature coefficient of 10.2 ppm/°C is realised with temperature ranging from −40°C to 140°C, and a power supply rejection ratio of 58 dB is achieved with a maximum supply current of 27 µA. The active area of the presented BGR is 160 × 140 µm2.

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency.

A novel high-order curvature-compensated CMOS bandgap voltage reference (BGR) is proposed in CSMC 0.5μm CMOS process. By adding a piecewise-curvature current in the low temperature region and a piecewise-curvature current in the high temperature region to a conventional BGR, the proposed high-order curvature-compensated BGR achieves a reference voltage with lower temperature coefficient (TC). Simulation results show that the TC of the proposed high-order curvature-compensated BGR is only 0.62ppm/°C while the TC of the conventional BGR is about 2.82ppm/°C. The proposed high-order curvature-compensated BGR achieves the power supply rejection ratio (PSRR) of −53.98dB, −53.97dB, −52.84dB, −39.097dB and −21.75dB at 10Hz, 1kHz, 10kHz, 100kHz and 1MHz respectively.

This paper presents a low-noise two-stage operation amplifier design procedure based on standard CMOS process. Unlike the previous researches that depict the design flow based on some simple circuit topologies for simplicity, this paper adopts the folded cascade input and Class AB output two-stage operational amplifier that is more admitted by academia and widely used into industry. This presented procedure begins with the key noise requirement to firstly determine the input difference pair whose transconductance is the most important parameter related to other electrical characters. Then the expressions and relationships of other parameters (such as slew rate, bandwidth, gain, phase margin, power consumption and signal swing) are derived under the constraint of noise requirement. Besides that, all sizes of devices are confirmed considering chip area, matching relation and layout. The low noise amplifier under the guidance of this proposed design procedure is implemented on a standard 0.18μm CMOS process. The measured results and simulation are closed agree with the expect results. So this design procedure offers designers an efficient way from electrical characters to key devices sizes based on the common operation amplifier circuit.

10 - Basic analog electronics: Operational amplifiers

The temperature coefficient (TC) of n-type polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this paper. The relationship between the TC and the activation energy is observed and explained. From the experimental results, it is also found that TC is not sensitive to the deviation of the laser crystallization energy. On the contrary, channel width can effectively modulate the TC of TFTs. By using the diode-connected poly-Si TFTs with different channel widths, the first voltage reference circuit with temperature compensation for precise analog circuit design on glass substrate is proposed and realized. From the experimental results in a low-temperature poly-Si process, the output voltage of voltage reference circuit with temperature compensation exhibits a very low TC of 195 ppm/degC , between 25degC and 125degC. The proposed voltage reference circuit with temperature compensation can be applied to design precise analog circuits for system-on-panel or system-on-glass applications, which enables the analog circuits to be integrated in the active-matrix liquid crystal display panels.

A novel 79-nW CMOS-only subthreshold voltage reference with 328-mV output voltage, which works down to 0.8-V supply voltage, is presented in this brief. In order to reduce the area and power consumption, the proposed circuit avoids the use of resistors and bipolar transistors. A current subtracting technique is proposed to realize the temperature compensation of reference current. Instead of the op-amp in traditional circuits, some cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). A novel structure consisting of a 1.8-V MOS transistor and a 3.3-V MOS transistor is utilized to accomplish the voltage temperature compensation and to further reduce the power consumption of VREF generator. The proposed voltage reference was fabricated in 0.18- ${\mu }\text{m}$ CMOS process. The measured results show that the temperature coefficient of the output voltage is 33.8 ppm/°C in the range from 10 °C to 100 °C, the PSRR is −55 dB @ 100 Hz at 1.2-V power supply, and the line regulation is 0.21%/V in a supply voltage range of 0.8 to 3.4 V. What is more, the power dissipation is 79 nW, and the chip area is 0.01 mm2. It is suitable for low-power applications.

This paper analyzed the factor of bias drift of quartz vibratory gyroscope, proposed the method of improving bias stability of quartz vibratory gyroscope and designed an interface ASIC of quartz vibratory gyroscope. The bias instability is generated by characteristic of noise in the detecting circuit and the quantity of the driving single in the exciting circuit. We propose a sine-wave exciting circuit which has lower phase noise than the traditional exciting approach. An operational amplifier with low noise and offset voltage temperature coefficient is designed to decrease the bias instability. The interface ASIC integrated on a 5×4.4 mm2 chip with 0.5 μm CMOS process has 40mW power supply, 18nV/Hz1/2 equivalent input noise density, and 0.8°/hour root Allan variance.